[1] H. Chen and D. D.-U. Li, “Multichannel, low nonlinearity time-todigital converters based on 20 and 28 nm FPGAs,” IEEE Trans. Ind.Electron., vol. 66, no. 4, pp. 3265–3274, Apr. 2019.
[2] Y. Wang, Q. Cao, and C. Liu, “A multi-chain merged tapped delay linefor high precision time-to-digital converters in FPGAs,” IEEE Trans.Circuits Syst., II, Exp. Briefs, vol. 65, no. 1, pp. 96–100, Jan. 2018.
[3] P. Chen, Y.-Y. Hsiao, Y.-S. Chung, W. X. Tsai, and J.-M. Lin, “A 2.5-psbin size and 6.7-ps resolution FPGA time-to-digital converter based ondelay wrapping and averaging,” IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 25, no. 1, pp. 114–124, Jan. 2017.
[4] R. Szplet, P. Kwiatkowski, K. Ró˙ zyc, Z. Jachna, and T. Sondej,“Picosecond-precision multichannel autonomous time and frequencycounter,” Rev. Sci. Instrum., vol. 88, no. 12, Dec. 2017, Art. no. 125101.
[5] Q. Shen et al., “A multi-chain measurements averaging TDC implemented in a 40 nm FPGA,” in Proc. 19th IEEE-NPSS Real Time Conf.RT-Conf. Rec., May 2014, pp. 1–3.
[6] Q. Shen et al., “A 1.7 ps equivalent bin size and 4.2 ps RMS FPGATDC based on multichain measurements averaging method,” IEEETrans. Nucl. Sci., vol. 62, no. 3, pp. 947–954, Jun. 2015.
[7] X. Qin, L. Wang, D. Liu, Y. Zhao, X. Rong, and J. Du, “A 1.15-ps binsize and 3.5-ps single-shot precision time-to-digital converter with onboard offset correction in an FPGA,” IEEE Trans. Nucl. Sci., vol. 64,no. 12, pp. 2951–2957, Dec. 2017.
[8] R. Szplet, D. Sondej, and G. Grzeda, “Subpicosecond-resolution timeto-digital converter with multi-edge coding in independent codinglines,” in Proc. IEEE Int. Instrum. Meas. Technol. Conf. (I2MTC),May 2014, pp. 747–751.
[9] C. Liu, Y. Wang, P. Kuang, D. Li, and X. Cheng, “A 3.9 ps RMSresolution time-To-digital converter using dual-sampling method onKintex ultrascale FPGA,” in Proc. IEEE-NPSS Real Time Conf. RT,Jun. 2016, pp. 1–3.
[10] Y. Wang and C. Liu, “A 3.9 ps time-interval RMS precision time-todigital converter using a dual-sampling method in an ultrascale FPGA,”IEEE Trans. Nucl. Sci., vol. 63, no. 5, pp. 2617–2621, Oct. 2016.
[11] Y. Wang and C. Liu, “A 4.2 ps time-interval RMS resolution time-todigital converter using a bin decimation method in an ultrascale FPGA,”IEEE Trans. Nucl. Sci., vol. 63, no. 5, pp. 2632–2638, Oct. 2016.
[12] J. Kalisz, “Review of methods for time interval measurementswith picosecond resolution,” Metrologia, vol. 41, no. 1, pp. 17–32,Feb. 2004.
[13] A. Rivetti, “Fast front-end electronics for semiconductor trackingdetectors: Trends and perspectives,” Nucl. Instrum. Methods Phys.Res. A, Accel. Spectrom. Detect. Assoc. Equip., vol. 765, pp. 202–208,Nov. 2014.
[14] Z. Cheng, X. Zheng, M. J. Deen, and H. Peng, “Recent developmentsand design challenges of high-performance ring oscillator CMOS timeto-digital converters,” IEEE Trans. Electron Devices, vol. 63, no. 1,pp. 235–251, Jan. 2016.
[15] S. Henzler, Time-to-Digital Converters, vol. 29. Dordrecht,The Netherlands: Springer, 2010.
[16] R. Szplet, “Time-to-digital converters,” in Design, Modeling and Testing of Data Converters, P. Carbone, S. Kiaei, and F. Xu, Eds. Berlin,Germany: Springer, 2014, pp. 211–246.
[17] P. Napolitano, A. Moschitta, and P. Carbone, “A survey on time intervalmeasurement techniques and testing methods,” in Proc. IEEE Instrum.Meas. Technol. Conf., May 2010, pp. 181–186.
[18] L. Bengtsson, “Embedded Vernier TDC with sub-nano second resolution using fractional-N PLL,” Measurement, vol. 108, pp. 48–54,Oct. 2017.
[19] M. Abbas and K. Khalil, “A 23 ps resolution Time-to-Digital converterimplemented on low-cost FPGA platform,” in Proc. Int. Symp. Signals,Circuits Syst. (ISSCS), Jul. 2015, pp. 1–4.
[20] N. Lusardi and A. Geraci, “8-channels high-resolution TDC in FPGA,”in Proc. IEEE Nucl. Sci. Symp. Med. Imag. Conf., Oct./Nov. 2015,pp. 1–2.
[21] C. Liu and Y. Wang, “A 128-channel, 710 M samples/second, and lessthan 10 ps RMS resolution time-to-digital converter implemented in aKintex-7 FPGA,” IEEE Trans. Nucl. Sci., vol. 62, no. 3, pp. 773–783,Jun. 2015.
[22] R. Szplet, Z. Jachna, P. Kwiatkowski, and K. Rozyc, “A 2.9 psequivalent resolution interpolating time counter based on multiple independent coding lines,” Meas. Sci. Technol., vol. 24, no. 3, Mar. 2013,Art. no. 035904.
[23] W. Pan, G. Gong, and J. Li, “A 20-ps time-to-digital converter (TDC)implemented in field-programmable gate array (FPGA) with automatic temperature correction,” IEEE Trans. Nucl. Sci., vol. 61, no. 3,pp. 1468–1473, Jun. 2014.
[24] Y. Yao, Z. Wang, H. Lu, L. Chen, and G. Jin, “Design of timeinterval generator based on hybrid counting method,” Nucl. Instrum.Methods Phys. Res. A, Accel., Spectrometers, Detectors AssociatedEquip., vol. 832, pp. 103–107, Oct. 2016.
[25] R. Machado, L. A. Rocha, and J. Cabral, “A novel synchronizer for a17.9 ps nutt time-to-digital converter implemented on FPGA,” in Proc.AEIT Int. Annu. Conf., Oct. 2018, pp. 1–6.
[26] R. A. Dias et al., “Real-time operation and characterization of a highperformance time-based accelerometer,” J. Microelectromech. Syst.,vol. 24, no. 6, pp. 1703–1711, Dec. 2015.
[27] R. Szplet, R. Szymanowski, and D. Sondej, “Measurement uncertaintyof precise interpolating time counters,” IEEE Trans. Instrum. Meas., tobe published.
[28] J.-P. Jansson, A. Mantyniemi, and J. Kostamovaara, “Multiplying delaylocked loop (MDLL) in time-to-digital conversion,” in Proc. IEEEInstrum. Meas. Technol. Conf., May 2009, pp. 1226–1231.
[29] R. Van De Plassche, “Specifications of converters,” in IntegratedAnalog-To-Digital and Digital-To-Analog Converters. Boston, MA,USA: Springer, 2003, pp. 57–64.
[30] S. Cova and M. Bertolaccini, “Differential linearity testing and precision calibration of multichannel time sorters,” Nucl. Instrum. Methods,vol. 77, no. 2, pp. 269–276, Jan. 1970.
[31] Z. Jachna, R. Szplet, P. Kwiatkowski, and K. Ró˙ zyc, “Permanentlycalibrated interpolating time counter,” Meas. Sci. Technol., vol. 26,no. 1, Jan. 2015, Art. no. 015006.
[32] J. Y. Won and J. S. Lee, “Time-to-digital converter using a tuned-delayline evaluated in 28-, 40-, and 45-nm FPGAs,” IEEE Trans. Instrum.Meas., vol. 65, no. 7, pp. 1678–1689, Jul. 2016.
[33] J. Zhang and D. Zhou, “A new delay line loops shrinking time-todigital converter in low-cost FPGA,” Nucl. Instrum. Methods Phys.Res. A, Accel., Spectrom., Detect., Assoc. Equip., vol. 771, pp. 10–16,Jan. 2015.
[34] K. Cui, Z. Ren, X. Li, Z. Liu, and R. Zhu, “A high-linearity, ringoscillator-based, Vernier time-to-digital converter utilizing carry chainsin FPGAs,” IEEE Trans. Nucl. Sci., vol. 64, no. 1, pp. 697–704,Jan. 2017.
[35] M. Arkani, “A high performance digital time interval spectrometer:An embedded, FPGA-based system with reduced dead time behaviour,”Metrol. Meas. Syst., vol. 22, no. 4, pp. 601–619, Dec. 2015.
[36] Q. Guo, R. Feng, Y. Wu, and N. Yu, “Measurement of the AFDXswitch latency based on FPGA,” in Proc. IEEE Int. Conf. Aircr. UtilitySyst. (AUS), Oct. 2016, pp. 45–49.
[37] D. N. Grigoriev, P. V. Kasyanenko, E. A. Kravchenko, A. G. Shamov,and A. A. Talyshev, “A 32-channel 840 Msps TDC based on alteracyclone III FPGA,” J. Instrum., vol. 12, no. 8, 2017, Art. no. C08025.
[38] D. Calvo, “1 ns time to digital converters for the KM3NeT data readoutsystem,” in Proc. AIP Conf., vol. 1630, no. 2014, pp. 98–101.
[39] Z. Li et al., “Development of an integrated four-channel fast avalanchephotodiode detector system with nanosecond time resolution,” Nucl.Instrum. Methods Phys. Res. A, Accel. Spectrom. Detect. Assoc. Equip.,vol. 870, pp. 43–49, Oct. 2017.
[40] A. Balla et al., “The characterization and application of a low resourceFPGA-based time to digital converter,” Nucl. Instrum. Methods Phys.Res. A, Accel. Spectrom. Detect. Assoc. Equip., vol. 739, pp. 75–82,Mar. 2014.
[41] Y. Sano, Y. Horii, M. Ikeno, O. Sasaki, M. Tomoto, and T. Uchida,“Subnanosecond time-to-digital converter implemented in a Kintex-7FPGA,” Nucl. Instrum. Methods Phys. Res. A, Accel. Spectrom. Detect.Assoc. Equip., vol. 874, pp. 50–56, Dec. 2017.
[42] H. Huang and W. Chou, “Hysteresis switch adaptive velocity evaluationand high-resolution position subdivision detection based on FPGA,”IEEE Trans. Instrum. Meas., vol. 64, no. 12, pp. 3387–3395, Dec. 2015.
[43] F. Huan-Huan, C. Ping, L. Shu-Bin, and A. Qi, “TOT measurementimplemented in FPGA TDC,” Chin. Phys. C, vol. 39, no. 11, 2015,Art. no. 116101.
[44] W. Yonggang, C. Xinyi, L. Deng, Z. Wensong, and L. Chong, “A lineartime-over-threshold digitizing scheme and its 64-channel DAQ prototype design on FPGA for a continuous crystal PET detector,” IEEETrans. Nucl. Sci., vol. 61, no. 1, pp. 99–106, Feb. 2014.
[45] T. Xiang et al., “A 56-ps multi-phase clock time-to-digital convertorbased on Artix-7 FPGA,” in Proc. 19th IEEE-NPSS Real Time Conf.,May 2014, pp. 1–4.MACHADO et al.: RECENT DEVELOPMENTS AND CHALLENGES IN FPGA-BASED TDCs 4219[46] Z. Song, Y. Wang, and J. Kuang, “A 256-channel, high throughputand precision time-to-digital converter with a decomposition encodingscheme in a Kintex-7 FPGA,” J. Instrum., vol. 13, no. 5, May 2018,Art. no. P05012.
[47] Y. Wang, P. Kuang, and C. Liu, “A 256-channel multi-phase clocksampling-based time-to-digital converter implemented in a Kintex-7FPGA,” in Proc. IEEE Int. Instrum. Meas. Technol. Conf., May 2016,pp. 1–5.
[48] B. Qi et al., “A compact readout electronics for the ground station ofa quantum communication satellite,” IEEE Trans. Nucl. Sci., vol. 62,no. 3, pp. 883–888, Jun. 2015.
[49] W.-S. Choong, F. Abu-Nimeh, W. W. Moses, Q. Peng, C. Q. Vu, andJ.-Y. Wu, “A front-end readout detector board for the OpenPET electronics system,” J. Instrum., vol. 10, no. 8, Aug. 2015, Art. no. T08002.
[50] V. L. Dinh, X. T. Nguyen, and H.-J. Lee, “A new FPGA implementation of a time-to-digital converter supporting run-time estimation ofoperating condition variation,” in Proc. IEEE Int. Symp. Circuits Syst.(ISCAS), May 2018, pp. 1–4.
[51] N. Franch, O. Alonso, J. Canals, A. Vilà, and A. Dieguez, “A low costfluorescence lifetime measurement system based on SPAD detectorsand FPGA processing,” in Proc. Conf. Design Circuits Integr. Syst.(DCIS), 2016, pp. 1–6.
[52] L.-Y. Hsu and J.-L. Huang, “A multi-channel FPGA-based time-todigital converter,” in Proc. IEEE 21st Int. Mixed-Signal Test. Workshop(IMSTW), Jul. 2016, pp. 1–4.
[53] H. Y. T. To et al., “A novel programmable on-chip voltage droopdetector for FPGA applications,” in Proc. IEEE 66th Electron. Compon.Technol. Conf. (ECTC), May/Jun. 2016, pp. 2009–2015.
[54] H. Chen, Y. Zhang, and D. D.-U. Li, “A low nonlinearity, missing-codefree time-to-digital converter based on 28-nm FPGAs with embeddedbin-width calibrations,” IEEE Trans. Instrum. Meas., vol. 66, no. 7,pp. 1912–1921, Jul. 2017.
[55] K. Katoh et al., “A small chip area stochastic calibration for TDCusing ring oscillator,” J. Electron. Test., vol. 30, no. 6, pp. 653–663,Dec. 2014.
[56] D. R. E. Gnad, F. Oboril, S. Kiamehr, and M. B. Tahoori, “An experimental evaluation and analysis of transient voltage fluctuations inFPGAs,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 26,no. 10, pp. 1817–1830, Oct. 2018.
[57] G. Cao, H. Xia, and N. Dong, “An 18-ps TDC using timing adjustment and bin realignment methods in a cyclone-IV FPGA,” Rev. Sci.Instrum., vol. 89, no. 5, 2018, Art. no. 054707.
[58] F. Nogrette et al., “Characterization of a detector chain using a FPGAbased time-to-digital converter to reconstruct the three-dimensionalcoordinates of single particles at high flux,” Rev. Sci. Instrum., vol. 86,no. 11, Nov. 2015, Art. no. 113105.
[59] J. Jung, Y. Choi, K. B. Kim, S. Lee, and H. J. Choe, “An improvedtime over threshold method using bipolar signals,” Phys. Med. Biol.,vol. 63, no. 13, Jun. 2018, Art. no. 135002.
[60] E. Venialgo et al., “An order-statistics-inspired, fully-digital readout approach for analog SiPM arrays,” in Proc. IEEE Nucl. Sci.Symp., Med. Imag. Conf. Room-Temp. Semiconductor Detect. Workshop(NSS/MIC/RTSD), Oct./Nov. 2016, pp. 1–5.
[61] J. Michel et al., “Electronics for the RICH detectors of the HADESand CBM experiments,” J. Instrum., vol. 12, no. 1, Jan. 2017,Art. no. C01072.
[62] E. Arabul, J. Rarity, and N. Dahnoun, “FPGA based fast integratedreal-time multi coincidence counter using a time-to-digital converter,”in Proc. 7th Medit. Conf. Embedded Comput. (MECO), Jun. 2018,pp. 1–4.
[63] A. T. Eshghi, S. Lee, M. K. Sadoughi, C. Hu, Y.-C. Kim, and J.-H. Seo,“Generic high resolution PET detector block using 12×12 SiPM array,”Smart Mater. Struct., vol. 26, no. 10, Oct. 2017, Art. no. 105037.
[64] N. Lusardi, A. Palmucci, and A. Geraci, “Fully-migratable TDC architecture for FPGA devices,” in Proc. IEEE Nucl. Sci. Symp., Med. Imag.Conf. Room-Temp. Semiconductor Detect. Workshop (NSS/MIC/RTSD),Oct./Nov. 2016, pp. 1–3.
[65] S. Grzelak, L. Wyd´ zgowski, J. Czoków, D. Chaberski, and M. Zieli´ nski,“High precision E effect measurement with the use of ultrasonicwave-time-of-flight method,” Przegla˛d Elektrotechniczny, vol. 1, no. 11,pp. 85–88, Nov. 2016.
[66] W. Pan, G. Gong, Q. Du, H. Li, and J. Li, “High resolution distributedtime-to-digital converter (TDC) in a white rabbit network,” Nucl.Instrum. Methods Phys. Res. A, Accel. Spectrom. Detect. Assoc. Equip.,vol. 738, pp. 13–19, Feb. 2014.
[67] N. Lusardi, A. Geraci, J. Marjanoviˇ c, and M. Gustin, “High-resolutionTDL-TDC system for MTCA.4 standard,” in Proc. IEEE Nucl. Sci.Symp., Med. Imag. Conf. Room-Temp. Semiconductor Detect. Workshop(NSS/MIC/RTSD), Oct./Nov. 2016, pp. 1–4.
[68] S. Grzelak, M. Kowalski, J. Czoków, and M. Zieli´ nski, “High resolutiontime-interval measurement systems applied to flow measurement,”Metrol. Meas. Syst., vol. 21, no. 1, pp. 77–84, Mar. 2014.
[69] B. Neumeier and D. Schmitt-Landsiedel, “Online condition measurement of high power solid state laser cutting optics using ultrasoundsignals,” Phys. Procedia, vol. 56, pp. 1252–1260, Jan. 2014.
[70] T. Polzer, F. Huemer, and A. Steininger, “Measuring metastability usinga time-to-digital converter,” in Proc. IEEE 20th Int. Symp. DesignDiagnostics Electron. Circuits Syst. (DDECS), Apr. 2017, pp. 116–121.
[71] R. Szplet, P. Kwiatkowski, K. Ró˙ zyc, M. Sawicki, and Z. Jachna,“Modular time interval counter,” in Proc. Eur. Freq. Time Forum(EFTF), Jun. 2014, pp. 494–497.
[72] M. Pałka et al., “Multichannel FPGA based MVT system for highprecision time (20 ps RMS) and charge measurement,” J. Instrum.,vol. 12, no. 8, Aug. 2017, Art. no. P08001.
[73] P. Deng et al., “Readout electronics of T0 detector in the external targetexperiment of CSR in HIRFL,” IEEE Trans. Nucl. Sci., vol. 65, no. 6,pp. 1315–1323, Jun. 2018.
[74] D. Yang et al., “Readout electronics of a prototype time-of-flight ioncomposition analyzer for space plasma,” Nucl. Sci. Techn., vol. 29,no. 4, p. 60, Apr. 2018.
[75] T. Polzer, F. Huemer, and A. Steininger, “Refined metastability characterization using a time-to-digital converter,” Microelectron. Rel.,vol. 80, pp. 91–99, Jan. 2018.
[76] E. Arabul, A. Girach, J. Rarity, and N. Dahnoun, “Precise multi-channeltiming analysis system for multi-stop LIDAR correlation,” in Proc.IEEE Int. Conf. Imag. Syst. Techn. (IST), Oct. 2017, pp. 1–6.
[77] R. Szplet, P. Kwiatkowski, Z. Jachna, and K. Ró˙ zyc, “Precise threechannel integrated time counter,” in Proc. Joint Conf. IEEE Int. Freq.Control Symp. Eur. Freq. Time Forum, Apr. 2015, pp. 575–578.
[78] H. Li, T. Xue, G. Gong, and J. Li, “The integration of FPGA TDCinside white rabbit node,” J. Instrum., vol. 12, no. 4, Apr. 2017,Art. no. P04020.
[79] S. Grzelak, J. Czoków, M. Kowalski, and M. Zieli´ nski, “Ultrasonicflow measurement with high resolution,” Metrol. Meas. Syst., vol. 21,no. 2, pp. 305–316, Jun. 2014.
[80] F. Huemer, T. Polzer, and A. Steininger, “Using a duplex time-to-digitalconverter for metastability characterization of an FPGA,” in Proc. IEEE21st Int. Symp. Design Diagnostics Electron. Circuits Syst. (DDECS),Apr. 2018, pp. 141–146.
[81] A. Aguilar et al., “Timing results using an FPGA-based TDC withlarge arrays of 144 SiPMs,” IEEE Trans. Nucl. Sci., vol. 62, no. 1,pp. 12–18, Feb. 2015.
[82] Y. Wang, J. Kuang, C. Liu, and Q. Cao, “A 3.9-ps RMS precision timeto-digital converter using ones-counter encoding scheme in a Kintex-7 FPGA,” IEEE Trans. Nucl. Sci., vol. 64, no. 10, pp. 2713–2718,Oct. 2017.
[83] Y. Wang and C. Liu, “A nonlinearity minimization-oriented resourcesaving time-to-digital converter implemented in a 28 nm XilinxFPGA,” IEEE Trans. Nucl. Sci., vol. 62, no. 5, pp. 2003–2009,Oct. 2015.
[84] Y. Wang, J. Kuang, C. Liu, Q. Cao, and D. Li, “A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000field programmable gate array,” Nucl. Instrum. Methods Phys. Res.A, Accel. Spectrom. Detect. Assoc. Equip., vol. 847, pp. 61–66,Mar. 2017.
[85] Q. Cao, Y. Wang, and C. Liu, “A combination of multiple channels ofFPGA based time-to-digital converter for high time precision,” in Proc.IEEE Nucl. Sci. Symp., Med. Imag. Conf. Room-Temp. SemiconductorDetect. Workshop (NSS/MIC/RTSD), Oct./Nov. 2016, pp. 1–3.
[86] P. Chen, Y.-Y. Hsiao, and Y.-S. Chung, “A high resolution FPGATDC converter with 2.5 ps bin size and -3.79~6.53 LSB integralnonlinearity,” in Proc. 2nd Int. Conf. Intell. Green Building Smart Grid(IGBSG), Jun. 2016, pp. 1–5.
[87] C. Ugur, S. Linev, J. Michel, T. Schweitzer, and M. Traxler,“A novel approach for pulse width measurements with a high precision(8 ps RMS) TDC in an FPGA,” J. Instrum., vol. 11, no. 1, 2016,Art. no. C01046.
[88] A. Tontini, L. Gasparini, L. Pancheri, and R. Passerone, “Design andcharacterization of a low-cost FPGA-based TDC,” IEEE Trans. Nucl.Sci., vol. 65, no. 2, pp. 680–690, Feb. 2018.4220 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 68, NO. 11, NOVEMBER 2019[89] J. Y. Won, S. I. Kwon, H. S. Yoon, G. B. Ko, J.-W. Son, and J. S. Lee,“Dual-phase tapped-delay-line time-to-digital converter with on-thefly calibration implemented in 40 nm FPGA,” IEEE Trans. Biomed.Circuits Syst., vol. 10, no. 1, pp. 231–242, Feb. 2016.
[90] S. Burri, H. Homulle, C. Bruschini, and E. Charbon, “LinoSPAD:A time-resolved 256 × 1 CMOS SPAD line sensor system featuring64 FPGA-based TDC channels running at up to 8.5 giga-events persecond,” Proc. SPIE, vol. 9899, Apr. 2016, Art. no. 98990D.
[91] J. Zheng, P. Cao, D. Jiang, and Q. An, “Low-cost FPGA TDC withhigh resolution and density,” IEEE Trans. Nucl. Sci., vol. 64, no. 6,pp. 1401–1408, Jun. 2017.
[92] S. Guo, Y. Wang, N. Li, J. Diao, and L. Chen, “Multi-chain timeinterval measurement method utilizing the dedicated carry chain ofFPGA,” in Proc. 7th IEEE Int. Conf. Electron. Inf. Emergency Commun.(ICEIEC), Jul. 2017, pp. 489–492.
[93] D. Chaberski, R. Frankowski, M. Zieli´ nski, and Ł. Zaworski, “Multipletapped-delay-line hardware-linearisation technique based on wire loadregulation,” Measurement, vol. 92, pp. 103–113, Oct. 2016.
[94] N. Lusardi, J. W. N. Los, R. B. M. Gourgues, G. Bulgarini, andA. Geraci, “Photon counting with photon number resolution throughsuperconducting nanowires coupled to a multi-channel TDC in FPGA,”Rev. Sci. Instrum., vol. 88, no. 3, 2017, Art. no. 035003.
[95] N. Lusardi, A. Abba, F. Caponio, and A. Geraci, “Quantization noisein non-homogeneous calibration table of a TCD implemented inFPGA,” in Proc. IEEE Nucl. Sci. Symp. Med. Imag. Conf. (NSS/MIC),Nov. 2014, pp. 1–5.
[96] Y. Wang, C. Liu, X. Cheng, and D. Li, “Spartan-6 FPGA based 8-channel time-to-digital converters for TOF-PET systems,” in Proc.IEEE Nucl. Sci. Symp. Med. Imag. Conf. (NSS/MIC), Oct./Nov. 2016,pp. 1–3.
[97] J. Torres et al., “Time-to-digital converter based on FPGA with multiplechannel capability,” IEEE Trans. Nucl. Sci., vol. 61, no. 1, pp. 107–114,Feb. 2014.
[98] D. Chaberski, “Time-to-digital-converter based on multiple-tappeddelay-line,” Measurement, vol. 89, pp. 87–96, Jul. 2016.
[99] H. Homulle, F. Regazzoni, and E. Charbon, “200 MS/s ADC implemented in a FPGA employing TDCs,” in Proc. ACM/SIGDA Int. Symp.Field-Program. Gate Arrays, 2015, pp. 228–235.
[100] S. Y. Wang, J. Wu, S. H. Yao, and W. C. Chang, “A field-programmablegate array (FPGA) TDC for the Fermilab seaquest (E906) experimentand its test with a novel external wave union launcher,” IEEE Trans.Nucl. Sci., vol. 61, no. 6, pp. 3592–3598, Dec. 2014.
[101] P. Moskal et al., “A novel method based solely on field programmable gate array (FPGA) units enabling measurement of time andcharge of analog signals in positron emission tomography (PET),” BioAlgorithms Med-Syst., vol. 10, no. 1, pp. 41–45, 2014.
[102] T. Chujo et al., “Experimental verification of timing measurementcircuit with self-calibration,” in Proc. 19th Annu. Int. Mixed-Signals,Sensors, Syst. Test Workshop, vol. 1, Sep. 2014, pp. 1–6.
[103] R. Narasimman, A. Prabhakar, and N. Chandrachoodan, “Implementation of a 30 ps resolution time to digital converter in FPGA,” in Proc.Int. Conf. Electron. Design, Comput. Netw. Automated Verification(EDCAV), Jan. 2015, pp. 12–17.
[104] A. Aguilar et al., “Optimization of a time-to-digital converter and acoincidence map algorithm for TOF-PET applications,” J. Syst. Archit.,vol. 61, no. 1, pp. 40–48, 2015.
[105] A. Aguilar et al., “Time of flight measurements based on FPGA using abreast dedicated PET,” J. Instrum., vol. 9, no. 5, 2014, Art. no. C05012.
[106] A. Aguilar et al., “Time of flight measurements based on FPGA andSiPMs for PET–MR,” Nucl. Instrum. Methods Phys. Res. A, Accel.Spectrom. Detect. Assoc. Equip., vol. 734, pp. 127–131, Jan. 2014.
[107] N. Lusardi, F. Garzetti, G. Bulgarini, R. B. M. Gourgues, J. W. N. Los,and A. Geraci, “Single photon counting through multi-channel TDCin programmable logic,” in Proc. IEEE Nucl. Sci. Symp., Med. Imag.Conf. Room-Temp. Semiconductor Detect. Workshop (NSS/MIC/RTSD),Oct./Nov. 2016, pp. 1–4.
[108] Y.-C. Chen, H.-C. Chang, and H. Chen, “Two-dimensional multiplyaccumulator for classification of neural signals,” IEEE Access, vol. 6,pp. 19714–19725, 2018.
[109] J. Wu and Z. Shi, “The 10-ps wave union TDC: Improving FPGA TDCresolution beyond its cell delay,” in Proc. IEEE Nucl. Sci. Symp. Conf.Rec., Oct. 2008, pp. 3440–3446.
[110] C. U˘ gur, G. Korcyl, J. Michel, M. Penschuk, and M. Traxler, “264channel TDC platform applying 65 channel high precision (7.2 psRMS)FPGA based TDCs,” in Proc. IEEE Nordic-Medit. Workshop TimeDigit. Converters (NoMe TDC), Oct. 2013, pp. 1–5.
[111] N. Lusardi, M. Luciani, and A. Geraci, “Single-chain 4-channelshigh-resolution multi-hit TDC in FPGA,” in Proc. IEEE Nucl. Sci.Symp., Med. Imag. Conf. Room-Temp. Semiconductor Detect. Workshop(NSS/MIC/RTSD), Oct./Nov. 2016, pp. 1–4.
[112] J. Kuang, Y. Wang, Q. Cao, and C. Liu, “Implementation of a highprecision multi-measurement time-to-digital convertor on a Kintex-7FPGA,” Nucl. Instrum. Methods Phys. Res. A, Accel. Spectrom. Detect.Assoc. Equip., vol. 891, pp. 37–41, May 2018.
[113] R. Szplet, P. Kwiatkowski, Z. Jachna, and K. Ró´ zyc, “An eight-channel4.5-ps precision timestamps-based time interval counter in FPGA chip,”IEEE Trans. Instrum. Meas., vol. 65, no. 9, pp. 2088–2100, Sep. 2016.
[114] K. Cui, X. Li, Z. Liu, and R. Zhu, “Toward implementing multichannels, ring-oscillator-based, Vernier time-to-digital converter in FPGAs:Key design points and construction method,” IEEE Trans. Radiat.Plasma Med. Sci., vol. 1, no. 5, pp. 391–399, Sep. 2017.
[115] G. Grze˛da and R. Szplet, “Time interval measurement module implemented in SoC FPGA device,” Int. J. Electron. Telecommun., vol. 62,no. 3, pp. 237–246, Sep. 2016.
[116] M. Maamoun, I. S. Arami, R. Beguenane, A. Benbelkacem, andA. Meraghni, “A 3 ps resolution time-to-digital converter in low-costFPGA for laser rangefinder,” in Proc. World Congr. Eng., vol. 1, 2017,pp. 7–11.
[117] K. Cui, Z. Liu, R. Zhu, and X. Li, “FPGA-based high-performancetime-to-digital converters by utilizing multi-channels looped carrychains,” in Proc. Int. Conf. Field Program. Technol. (ICFPT),Dec. 2017, pp. 223–226.
[118] C.-C. Chen, C.-S. Hwang, Y. Lin, and G.-H. Chen, “Note: All-digitalpulse-shrinking time-to-digital converter with improved dynamicrange,” Rev. Sci. Instrum., vol. 87, no. 4, Apr. 2016, Art. no. 046104.
[119] C.-C. Chen, S.-H. Lin, and C.-S. Hwang, “An area-efficient CMOStime-to-digital converter based on a pulse-shrinking scheme,” IEEETrans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 3, pp. 163–167,Mar. 2014.
[120] Y. Liu et al., “A 6 ps resolution pulse shrinking Time-to-DigitalConverter as phase detector in multi-mode transceiver,” in Proc. IEEERadio Wireless Symp., Jan. 2008, pp. 163–166.
[121] L. Perktold and J. Christiansen, “A multichannel time-to-digital converter ASIC with better than 3 ps RMS time resolution,” J. Instrum.,vol. 9, no. 1, Jan. 2014, Art. no. C01060.
[122] I. Diehl et al., “Readout ASIC for fast digital imaging using SiPMsensors: Concept study,” in Proc. IEEE Nucl. Sci. Symp. Med. Imag.Conf. (NSS/MIC), Oct./Nov. 2015, pp. 1–3.
[123] J. Mauricio, D. Gascon, D. Ciaglia, S. Gómez, G. Fernández, andA. Sanuy, “MATRIX: A novel two-dimensional resistive interpolation15 ps time-to-digital converter ASIC,” in Proc. IEEE Nucl. Sci.Symp., Med. Imag. Conf. Room-Temp. Semiconductor Detect. Workshop(NSS/MIC/RTSD), Oct./Nov. 2016, pp. 1–3.
[124] A. Pokhara, J. Agrawal, and B. Mishra, “Design of an all-digital, lowpower time-to-digital converter in 0.18 μm CMOS,” in Proc. 7th Int.Symp. Embedded Comput. Syst. Design (ISED), Dec. 2017, pp. 1–5.
[125] J. Wu, W. Zhang, X. Yu, Q. Jiang, L. Zheng, and W. Sun, “A hybridtime-to-digital converter based on residual time extraction and amplification,” Microelectron. J., vol. 63, pp. 148–154, May 2017.
[126] J. Wang et al., “Development of a time-to-digital converter ASICfor the upgrade of the ATLAS monitored drift tube detector,” Nucl.Instrum. Methods Phys. Res. A, Accel., Spectrometers, Detectors Associated Equip., vol. 880, pp. 174–180, Feb. 2018.
[127] R. Enomoto, T. Iizuka, T. Koga, T. Nakura, and K. Asada, “A 16-bit2.0-ps resolution two-step TDC in 0.18-μm CMOS utilizing pulseshrinking fine stage with built-in coarse gain calibration,” IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 27, no. 1, pp. 11–19,Jan. 2019.
[128] H. Molaei and K. Hajsadeghi, “A 5.3-ps, 8-b time to digital converterusing a new gain-reconfigurable time amplifier,” IEEE Trans. CircuitsSyst., II, Exp. Briefs, vol. 66, no. 3, pp. 352–356, Mar. 2019.
[129] T. Suwada, F. Miyahara, K. Furukawa, M. Shoji, M. Ikeno, andM. Tanaka, “Wide dynamic range FPGA-based TDC for monitoring atrigger timing distribution system in linear accelerators,” Nucl. Instrum.Methods Phys. Res. A, Accel. Spectrom. Detect. Assoc. Equip., vol. 786,pp. 83–90, Jun. 2015.
[130] Y. Sano, M. Tomoto, Y. Horii, O. Sasaki, T. Uchida, and M. Ikeno,“Development of a sub-nanosecond time-to-digital converter based ona field-programmable gate array,” J. Instrum., vol. 11, no. 3, Mar. 2016,Art. no. C03053.MACHADO et al.: RECENT DEVELOPMENTS AND CHALLENGES IN FPGA-BASED TDCs 4221[131] Y. Sano et al., “Performances of typical high energy physics applications in flash-based field-programmable gate array under gammairradiation,” J. Instrum., vol. 12, no. 4, Apr. 2017, Art. no. C04002.
[132] M. Büchele, H. Fischer, F. Herrmann, and C. Schaffer,“The ARAGORN front-end—FPGA based implementation of atime-to-digital converter,” in Proc. IEEE Nucl. Sci. Symp., Med. Imag.Conf. Room-Temp. Semiconductor Detect. Workshop (NSS/MIC/RTSD),Oct./Nov. 2016, pp. 1–3.
[133] Y. Jia, C. Wang, H. Shi, and X. Liu, “Multi-channel high precisiontime digital converter system based on equivalent pulse counting,” inProc. Chin. Control Decis. Conf. (CCDC), Jun. 2018, pp. 5933–5938.
[134] J. Wu, “An FPGA wave union TDC for time-of-flight applications,” inProc. IEEE Nucl. Sci. Symp. Conf. Rec. (NSS/MIC), Oct./Nov. 2009,pp. 299–304.
[135] H. Menninga, C. Favi, M. W. Fishburn, and E. Charbon, “A multichannel, 10 ps resolution, FPGA-based TDC with 300 MS/s throughputfor open-source PET applications,” in Proc. IEEE Nucl. Sci. Symp.Conf. Rec., Oct. 2011, pp. 1515–1522.
[136] L. Zhao, X. Hu, S. Liu, J. Wang, and Q. An, “A 16-channel 15 psTDC implemented in a 65 nm FPGA,” in Proc. 18th IEEE-NPSS RealTime Conf., Jun. 2012, pp. 1–5.
[137] M. W. Fishburn, L. H. Menninga, C. Favi, and E. Charbon, “A 19.6 ps,FPGA-based TDC with multiple channels for open source applications,” IEEE Trans. Nucl. Sci., vol. 60, no. 3, pp. 2203–2208, Jun. 2013.
[138] Y.-H. Chen, “A high resolution FPGA-based merged delay line TDCwith nonlinearity calibration,” in Proc. IEEE Int. Symp. Circuits Syst.(ISCAS), May 2013, pp. 2432–2435.
[139] Q. Xi, F. Changqing, Z. Deliang, Z. Lei, L. Shubin, and A. Qi, “A lowdead time Vernier delay line TDC implemented in an actel flash-basedFPGA,” Nucl. Sci. Tech., vol. 24, no. 4, 2013, Art. no. 40403.
[140] N. Dutton et al., “Multiple-event direct to histogram TDC in 65 nmFPGA technology,” in Proc. 10th Conf. Ph.D. Res. Microelectron.Electron. (PRIME), Jun./Jul. 2014, pp. 1–5.
[141] J. P. Caram, J. Galloway, and J. S. Kenney, “Harmonic ring oscillatortime-to-digital converter,” in Proc. IEEE Int. Symp. Circuits Syst.(ISCAS), May 2015, pp. 161–164.
[142] R. Frankowski, M. Gurski, and P. Płóciennik, “Optical methods of thedelay cells characteristics measurements and their applications,” Opt.Quantum Electron., vol. 48, no. 3, p. 188, Mar. 2016.
[143] M. Zhang, H. Wang, and Y. Liu, “A 7.4 ps FPGA-based TDC with a1024-unit measurement matrix,” Sensors, vol. 17, no. 4, p. 865, 2017.
[144] Y.-H. Chen, “A counting-weighted calibration method for afield-programmable-gate-array-based time-to-digital converter,” Nucl.Instrum. Methods Phys. Res. A, Accel. Spectrom. Detect. Assoc. Equip.,vol. 854, pp. 61–63, May 2017.
[145] R. Szplet and K. Klepacki, “An FPGA-integrated time-to-digitalconverter based on two-stage pulse shrinking,” IEEE Trans. Instrum.Meas., vol. 59, no. 6, pp. 1663–1670, Jun. 2010.
[146] C. Chen, S. Meng, Z. Xia, G. Fang, and H. Yin, “Pulse shrinking timeto-digital converter for UWB application,” J. Electron., vol. 31, no. 3,pp. 180–186, 2014.
[147] J. Zhang and D. Zhou, “An 8.5-ps two-stage Vernier delay-line loopshrinking time-to-digital converter in 130-nm flash FPGA,” IEEETrans. Instrum. Meas., vol. 67, no. 2, pp. 406–414, Feb. 2018.
[148] K. R. Jeyashankar, M. Mahalley, and B. Amrutur, “A time-based lowvoltage body temperature monitoring unit,” in Proc. 27th Int. Conf.VLSI Design 13th Int. Conf. Embedded Syst., Jan. 2014, pp. 522–527.
[149] M. P. Mattada, S. M. Magadum, and H. Guhilot, “Identification ofhotspots on FPGA using time to digital converter and distributed tinysensors,” in Proc. 2nd Int. Symp. Phys. Technol. Sensors (ISPTS),Mar. 2015, pp. 235–239.
[150] N. Bulic, P. Dirnberger, and S. Silber, “New digital sensor design forrotor displacement measurement based on the coupled oscillators,” inProc. 5th Eur. DSP Educ. Res. Conf., Sep. 2012, pp. 247–251.
[151] E. Bergeron, M. Feeley, M.-A. Daigneault, and J. P. David, “Usingdynamic reconfiguration to implement high-resolution programmabledelays on an FPGA,” in Proc. Joint 6th Int. IEEE Northeast WorkshopCircuits Syst. TAISA Conf., Jun. 2008, pp. 265–268.
[152] F. Dadouche, T. Turko, W. Uhring, I. Malass, J. Bartringer, and J. LeNormand, “Design methodology of TDC on low cost FPGA targets,”in Proc. 9th Int. Conf. Sensor Technol. Appl. (SENSORCOMM), 2015,pp. 29–34.
[153] R. Machado, L. A. Rocha, and J. Cabral, “A novel synchronizer fora 17.9 ps Nutt Time-to-Digital Converter implemented on FPGA,” inProc. AEIT Int. Annu. Conf., Oct. 2018, pp. 1–6.

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