北京邮电大学砸彩蛋大作业
目录
- 设计任务要求
- 系统设计
- 仿真波形及分析
- 源程序
- 功能说明及资源利用情况
- 故障及问题分析
- 总结和结论
- 设计任务要求
基本要求：
1、8*8点阵中每2*2四个点为一组代表一个蛋的位置，共4*4个位置，与4*4矩阵键 盘位置对应；
2、 数码管DISP1和DISP0显示游戏者得分，DISP7和DISP6显示游戏时间；
3、 用SW7作为游戏机开关，打开开关SW7后游戏开始，此时DISP1和DISP0显示得分“00”，DISP7和DISP6显示游戏时间"00”；
4、 使用按键BTN3进入游戏状态，时间从“00”开始每秒正计时显示。点阵在随机位 置显示彩蛋，彩蛋颜色随机为红色，每只彩蛋显示时间为1秒；
5、 在彩蛋显示时间内，按动相应位置的按键表示击中彩蛋，游戏者得分；彩蛋被击中后四个亮点向四周扩散一圈以呈现爆炸效果，爆炸效果变化下图，如果彩蛋在点阵 边缘，爆炸扩散时只显示点阵范围内部分即可；
6、 击中红蛋加1分，得分同步显示在DISP1和DISP0；
7、 游戏时间已到“60”，则游戏结束，
9、 使用按键SW7可以重新进入新一轮游戏。
- 系统设计
- 设计框图
2.模块设计
1. 随机数生成模块
2.按键模块
3.矩阵显示模块
4.中枢判断模块
5.记分模块
6.计时模块
7.数码管显示模块
8.最终显示模块
总程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ZCD IS
PORT(CLKALL:IN STD_LOGIC;
START:IN STD_LOGIC;
ROW:IN STD_LOGIC_VECTOR(3 DOWNTO 0);--键盘行信号
COL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);--键盘列信号
SEGOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);--数码管阳极
CATOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);--数码管阴极
R: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);--点阵行信号
CR: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);--点阵红信号
CG: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);--点阵绿信号
V:OUT STD_LOGIC);--声音信号
END ZCD;
architecture s OF ZCD IS
SIGNAL TMP1:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL TMP2,TMP4,TMP5,TMP6,TMP8:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL TMP3,TMP7,Z1,Z2,vvv:STD_LOGIC;
SIGNAL TMP9:STD_LOGIC_VECTOR(1 DOWNTO 0);
signal Z3:STD_LOGIC_VECTOR(7 DOWNTO 0);
COMPONENT SJS1 --随机数
PORT(CLKSJS,RESET:IN STD_LOGIC;
SJS: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT KBD --键盘
PORT(CLKKBD:IN STD_LOGIC;
RR:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
C:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
K:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT JGE --中枢判断
PORT(JGCLK:IN STD_LOGIC;
SJS:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
KEY:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
JGE:OUT STD_LOGIC);
END COMPONENT;
COMPONENT DZ --点阵
PORT(CLKDZ,RESET:IN STD_LOGIC;
SJSIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
JGE:IN STD_LOGIC;
ROUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
COLR: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
COLG: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT SCORE --积分
PORT(ADD,CLK,RESET: IN STD_LOGIC;
SCOREOUT1,SCOREOUT2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT TIME0 --计时
PORT(CLK,RESET: IN STD_LOGIC;
TIMEOUT1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
TIMEOUT2:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
FIN:OUT STD_LOGIC);
END COMPONENT;
COMPONENT YMG --数码管显示
PORT(CLK,RESET:IN STD_LOGIC;
T1,T2,S1,S2:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SAO:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
SEG,CAT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT BAIWAN
PORT(CLK:IN STD_LOGIC;
CLKOUT:OUT STD_LOGIC);
END COMPONENT;
COMPONENT SM
PORT(CLK:IN STD_LOGIC;
CLK_OUT:OUT STD_LOGIC_VECTOR (1 DOWNTO 0));
END COMPONENT;
COMPONENT FIN
PORT(CLK,F1,VV:IN STD_LOGIC;
DZZ:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
FVV:OUT STD_LOGIC;
FDZ:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT YY
port( clk : in std_logic;
reset : in std_logic;
voices: out std_logic);
end component;
BEGIN
U1:KBD PORT MAP(CLKKBD => CLKALL, RR => ROW, C => COL, K => TMP1);
U2:SJS1 PORT MAP(CLKSJS => CLKALL, RESET => START, SJS => TMP2);
U3:JGE PORT MAP(JGCLK => CLKALL,SJS => TMP2, KEY => TMP1, JGE => TMP3);
U4:DZ PORT MAP(CLKDZ => CLKALL, RESET => START, SJSIN => TMP2, JGE => TMP3, ROUT => R, COLR => Z3, COLG => CG);
U5:BAIWAN PORT MAP(CLK => CLKALL, CLKOUT => TMP7);
U6:TIME0 PORT MAP(CLK => TMP7 ,RESET=>START, TIMEOUT1 => TMP4,TIMEOUT2=> TMP6,FIN=>Z1);
U7:SCORE PORT MAP(ADD => TMP3, CLK => CLKALL, RESET=> START, SCOREOUT1 => TMP5,SCOREOUT2 => TMP8);
U8:SM PORT MAP(CLK => CLKALL, CLK_OUT => TMP9);
U9:YMG PORT MAP(CLK => CLKALL, RESET=>START, T1 => TMP4, T2 => TMP6,S1 => TMP5,S2 => TMP8, SAO => TMP9 ,SEG => SEGOUT, CAT => CATOUT);
U10:YY PORT MAP(CLK=>CLKALL, RESET=>START,voices=>vvv);
U11:FIN PORT MAP(CLK=>CLKALL, F1=>Z1,VV=>vvv ,DZZ=>Z3,FDZ=>CR,FVV=>V);
END architecture s;
随机数模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SJS1 IS --随机数
PORT(CLKSJS,RESET:IN STD_LOGIC;
SJS: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END SJS1;
architecture s OF SJS1 IS
SIGNAL CLK1: STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL CLK3: STD_LOGIC;
SIGNAL TMP1: STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL TMP: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL CLKx: STD_LOGIC;
COMPONENT GS --高速计数器
PORT(CLK,CLEAR:IN STD_LOGIC;
CLK_OUT:OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END COMPONENT;
COMPONENT DDIV --分频器
PORT(CLK:IN STD_LOGIC;
CLKa:OUT STD_LOGIC);
END COMPONENT;
COMPONENT DIV2000 --0.5秒分频器
PORT(CLK:IN STD_LOGIC;
CLK_OUT:OUT STD_LOGIC);
END COMPONENT;
COMPONENT CATCH --截取器
PORT(CLK:IN STD_LOGIC;
RU:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CHU:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
BEGIN
U1:DDIV PORT MAP(CLK => CLKSJS, CLKa => CLKx);
U2:GS PORT MAP(CLK => CLKx, CLEAR => RESET, CLK_OUT=> TMP1);
U3:DIV2000 PORT MAP(CLK => CLKSJS, CLK_OUT => CLK3);
U4:CATCH PORT MAP(CLK=> CLK3, RU => TMP1, CHU => SJS);
END architecture s;
高速计数器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY GS IS
PORT(CLK,CLEAR:IN STD_LOGIC;
CLK_OUT:OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END GS;
ARCHITECTURE a OF GS IS
BEGIN
PROCESS(CLK,CLEAR)
VARIABLE TMP:STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
IF CLEAR = '1' THEN
TMP:= "0000"; CLK_OUT <="0000";
ELSIF CLK'EVENT AND CLK='1'
THEN
IF TMP = "1111"THEN TMP :="0000";
ELSE TMP:=TMP+1;
END IF;
CLK_OUT <= TMP;
END IF;
END PROCESS;
END a;
分频器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDIV IS
PORT(CLK:IN STD_LOGIC;
CLKa:OUT STD_LOGIC);
END DDIV;
ARCHITECTURE a OF DDIV IS
SIGNAL TMP1: INTEGER RANGE 0 TO 370;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'event AND CLK='1' THEN
IF TMP1<370 THEN
TMP1 <= TMP1+1;
ELSE
TMP1 <= 0;
END IF;
IF TMP1<190 THEN
CLKa <= '0';
ELSE
CLKa <= '1';
END IF;
END IF;
END PROCESS;
END a;
0.5s分频器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DIV2000 IS
PORT(CLK:IN STD_LOGIC;
CLK_OUT:OUT STD_LOGIC);
END DIV2000;
ARCHITECTURE a OF DIV2000 IS
SIGNAL TMP: INTEGER RANGE 0 TO 19999999;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'event AND CLK='1' THEN
IF TMP<19999999 THEN
TMP <= TMP+1;
ELSE
TMP <= 0;
END IF;
IF tmp<9999999 THEN
CLK_OUT <= '0';
ELSE
CLK_OUT <= '1';
END IF;
END IF;
END PROCESS;
END a;
截取器
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY CATCH IS
PORT(CLK: IN STD_LOGIC;
RU: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CHU: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END CATCH;
architecture s OF CATCH IS
BEGIN
Process(CLK,RU)
BEGIN
IF CLK'event AND CLK='1' THEN
CHU <= RU ;
END IF;
END Process;
END s;
键盘模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY KBD IS
PORT(CLKKBD:IN STD_LOGIC;
RR:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
C:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
K:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END KBD;
architecture s OF KBD IS
SIGNAL CLK1: STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL CLK2: STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT JSQ --行信号扫描计数
PORT(CLK:IN STD_LOGIC;
CLK_OUT:OUT STD_LOGIC_VECTOR (1 DOWNTO 0));
END COMPONENT;
COMPONENT COL --行信号扫描
PORT(a:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
CLK:IN STD_LOGIC;
l:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
i:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT KEY --对应按键
PORT(COL: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ROW: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLK: IN STD_LOGIC;
b: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
BEGIN
U1:JSQ PORT MAP(CLK => CLKKBD, CLK_OUT => CLK1);
U2:COL PORT MAP(a => CLK1, CLK => CLKKBD, l => CLK2, i => C);
U3:KEY PORT MAP(COL => CLK2, ROW => RR, CLK => CLKKBD, b => K);
END architecture s;
行信号扫描计数器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JSQ IS
PORT(CLK:IN STD_LOGIC;
CLK_OUT:OUT STD_LOGIC_VECTOR (1 DOWNTO 0));
END JSQ;
ARCHITECTURE a OF JSQ IS--键盘行信号扫描计数
SIGNAL TMP:STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF TMP = "11" THEN TMP<="00";
ELSE TMP<=TMP+1;
END IF;
CLK_OUT <= TMP;
END IF;
END PROCESS;
END a;
行信号扫描
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY COL IS
PORT(a:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
CLK:IN STD_LOGIC;
l:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
i:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COL;
architecture s OF COL IS--行信号扫描
SIGNAL TMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
Process(a)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
CASE a IS
WHEN "00" => TMP <="1110";
WHEN "01" => TMP <="1101";
WHEN "10" => TMP <="1011";
WHEN "11" => TMP <="0111";
END CASE;
END IF;
l<=TMP;
i<=TMP;
END Process;
END s;
对应按键
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY KEY IS
PORT(COL: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ROW: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLK: IN STD_LOGIC;
b: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END KEY;
architecture s OF KEY IS--键盘对应
BEGIN
Process(ROW,COL,CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF COL <= "0111" THEN
CASE ROW IS
WHEN "1110" => b <= "1111";--F
WHEN "1101" => b <= "1011";--b
WHEN "1011" => b <= "0111";--7
WHEN "0111" => b <= "0011";--3
WHEN OTHERS => NULL;
END CASE;
ELSIF COL <="1011" THEN
CASE ROW IS
WHEN "1110" => b <= "1110";--E
WHEN "1101" => b <= "1010";--A
WHEN "1011" => b <= "0110";--6
WHEN "0111" => b <= "0010";--2
WHEN OTHERS => NULL;
END CASE;
ELSIF COL <= "1101" THEN
CASE ROW IS
WHEN "1110" => b <= "1101";--d
WHEN "1101" => b <= "1001";--9
WHEN "1011" => b <= "0101";--5
WHEN "0111" => b <= "0001";--1
WHEN OTHERS => NULL;
END CASE;
ELSIF COL <= "1110" THEN
CASE ROW IS
WHEN "1110" => b <= "1100";--C
WHEN "1101" => b <= "1000";--8
WHEN "1011" => b <= "0100";--4
WHEN "0111" => b <= "0000";--0
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
END Process;
END s;
中枢判断模块
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY JGE IS
PORT(JGCLK:IN STD_LOGIC;
SJS:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
KEY:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
JGE:OUT STD_LOGIC);
END JGE;
architecture s OF JGE IS
SIGNAL TMP1: INTEGER RANGE 0 TO 1999999;
SIGNAL TMP2: STD_LOGIC;
BEGIN
Process(JGCLK,SJS,KEY)
BEGIN
IF JGCLK'event AND JGCLK='1' THEN
IF TMP1<1999999 THEN
TMP1 <= TMP1+1;
ELSE
TMP1 <= 0;
END IF;
IF TMP1<999999 THEN
TMP2 <= '0';
ELSE
TMP2 <= '1';
END IF;
END IF;
IF SJS = KEY THEN
JGE <= '0';
ELSE
JGE <= '1';
END IF;
END Process;
END s;
点阵显示模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DZ IS
PORT(CLKDZ,RESET:IN STD_LOGIC;
SJSIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
JGE:IN STD_LOGIC;
ROUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
COLR: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
COLG: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END DZ;
architecture s OF DZ IS
SIGNAL CLK1,CLK2: STD_LOGIC;
SIGNAL CLK3: STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT DZDIV10000
PORT(CLK:IN STD_lOGIC;
CLK_OUT: OUT STD_LOGIC);
END COMPONENT;
COMPONENT JSQ2 --点阵行信号扫描计数
PORT(CLK,CLEAR:IN STD_LOGIC;
CLK_OUT:OUT STD_LOGIC_VECTOR (2 DOWNTO 0));
END COMPONENT;
COMPONENT HXH --点阵行信号扫描
PORT(aa: IN STD_LOGIC_VECTOR(2 DOWNTO 0);--8 hang qiehuan
x: IN STD_LOGIC;
b: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT LXH --点阵列信号
PORT(a: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
p: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
q: IN STD_LOGIC;
x: IN STD_LOGIC;
cr: out std_logic_vector(7 downto 0);
cg: out std_logic_vector(7 downto 0));
END COMPONENT;
BEGIN
U1:DZDIV10000 PORT MAP(CLK => CLKDZ, CLK_OUT => CLK2);
U2:JSQ2 PORT MAP(CLK => CLKDZ, CLK_OUT => CLK3, CLEAR => RESET);
U3:HXH PORT MAP(aa => CLK3, x => CLKDZ, b => ROUT);
U4:LXH PORT MAP(a => SJSIN, p => CLK3, q => JGE, x => CLKDZ, cr => COLR, cg => COLG);
END architecture s;
秒分频器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DZDIV10000 IS
PORT(CLK:IN STD_LOGIC;
CLK_OUT:OUT STD_LOGIC);
END DZDIV10000;
ARCHITECTURE a OF DZDIV10000 IS
SIGNAL TMP: INTEGER RANGE 0 TO 9999999;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'event AND CLK='1' THEN
IF TMP<9999999 THEN
TMP <= TMP+1;
ELSE
TMP <= 0;
END IF;
IF tmp<4999999 THEN
CLK_OUT <= '0';
ELSE
CLK_OUT <= '1';
END IF;
END IF;
END PROCESS;
END a;
点阵行信号扫描计数器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JSQ2 IS
PORT(CLK,CLEAR:IN STD_LOGIC;
CLK_OUT:OUT STD_LOGIC_VECTOR (2 DOWNTO 0));
END JSQ2;
ARCHITECTURE a OF JSQ2 IS
SIGNAL TMP:STD_LOGIC_VECTOR (2 DOWNTO 0);
BEGIN
PROCESS(CLK,CLEAR)
BEGIN
IF CLEAR = '1' THEN
CLK_OUT <= "000";
ELSIF CLK'EVENT AND CLK='1' THEN
IF TMP="111" THEN TMP<="000";
ELSE TMP<=TMP+1;
END IF;
CLK_OUT <= TMP;
END IF;
END PROCESS;
END a;
点阵行信号扫描
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY HXH IS --点阵行信号扫描
PORT(aa: IN STD_LOGIC_VECTOR(2 DOWNTO 0);--8 hang qiehuan
x: IN STD_LOGIC;
b: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END HXH;
architecture s OF HXH IS
SIGNAL tmp : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
Process(aa)
BEGIN
IF x'event AND x='1' THEN
CASE aa IS
WHEN "000" => b <="01111111";
WHEN "001" => b <="10111111";
WHEN "010" => b <="11011111";
WHEN "011" => b <="11101111";
WHEN "100" => b <="11110111";
WHEN "101" => b <="11111011";
WHEN "110" => b <="11111101";
WHEN "111" => b <="11111110";
END CASE;
END IF;
END Process;
END s;
点阵列信号
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY LXH IS --点阵列信号
PORT(a: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
p: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
q: IN STD_LOGIC;
x: IN STD_LOGIC;
cr: out std_logic_vector(7 downto 0);
cg: out std_logic_vector(7 downto 0));
END LXH;
architecture s OF LXH IS
SIGNAL tmp : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
Process(x,a,p,q)
BEGIN
IF x'event AND x='1' THEN
IF q = '1' THEN
IF a <= "0000" THEN
CASE p IS
WHEN "000" => cr <="11000000";
WHEN "001" => cr <="11000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "0001" THEN
CASE p IS
WHEN "000" => cr <="00110000";
WHEN "001" => cr <="00110000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "0010" THEN
CASE p IS
WHEN "000" => cr <="00001100";
WHEN "001" => cr <="00001100";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "0011" THEN
CASE p IS
WHEN "000" => cr <="00000011";
WHEN "001" => cr <="00000011";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "0100" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="11000000";
WHEN "011" => cr <="11000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "0101" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00110000";
WHEN "011" => cr <="00110000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "0110" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00001100";
WHEN "011" => cr <="00001100";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "0111" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000011";
WHEN "011" => cr <="00000011";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "1000" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="11000000";
WHEN "101" => cr <="11000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "1001" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00110000";
WHEN "101" => cr <="00110000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "1010" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00001100";
WHEN "101" => cr <="00001100";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "1011" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000011";
WHEN "101" => cr <="00000011";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "1100" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="11000000";
WHEN "111" => cr <="11000000";
END CASE;
ELSIF a<= "1101" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00110000";
WHEN "111" => cr <="00110000";
END CASE;
ELSIF a<= "1110" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00001100";
WHEN "111" => cr <="00001100";
END CASE;
ELSIF a<= "1111" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000011";
WHEN "111" => cr <="00000011";
END CASE;
END IF;
ELSIF q = '0' THEN
IF a <= "0000" THEN
CASE p IS
WHEN "000" => cr <="00100000";
WHEN "001" => cr <="00100000";
WHEN "010" => cr <="11000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "0001" THEN
CASE p IS
WHEN "000" => cr <="01001000";
WHEN "001" => cr <="01001000";
WHEN "010" => cr <="00110000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "0010" THEN
CASE p IS
WHEN "000" => cr <="00010010";
WHEN "001" => cr <="00010010";
WHEN "010" => cr <="00001100";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "0011" THEN
CASE p IS
WHEN "000" => cr <="00000100";
WHEN "001" => cr <="00000100";
WHEN "010" => cr <="00000011";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "0100" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="11000000";
WHEN "010" => cr <="00100000";
WHEN "011" => cr <="00100000";
WHEN "100" => cr <="11000000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "0101" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00110000";
WHEN "010" => cr <="01001000";
WHEN "011" => cr <="01001000";
WHEN "100" => cr <="00110000";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "0110" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00001100";
WHEN "010" => cr <="00010010";
WHEN "011" => cr <="00010010";
WHEN "100" => cr <="00001100";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "0111" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000011";
WHEN "010" => cr <="00000100";
WHEN "011" => cr <="00000100";
WHEN "100" => cr <="00000011";
WHEN "101" => cr <="00000000";
WHEN "110" => cr <="00000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "1000" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="11000000";
WHEN "100" => cr <="00100000";
WHEN "101" => cr <="00100000";
WHEN "110" => cr <="11000000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "1001" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00110000";
WHEN "100" => cr <="01001000";
WHEN "101" => cr <="01001000";
WHEN "110" => cr <="00110000";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "1010" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00001100";
WHEN "100" => cr <="00010010";
WHEN "101" => cr <="00010010";
WHEN "110" => cr <="00001100";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "1011" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000011";
WHEN "100" => cr <="00000100";
WHEN "101" => cr <="00000100";
WHEN "110" => cr <="00000011";
WHEN "111" => cr <="00000000";
END CASE;
ELSIF a<= "1100" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="11000000";
WHEN "110" => cr <="00100000";
WHEN "111" => cr <="00100000";
END CASE;
ELSIF a<= "1101" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00110000";
WHEN "110" => cr <="01001000";
WHEN "111" => cr <="01001000";
END CASE;
ELSIF a<= "1110" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00001100";
WHEN "110" => cr <="00010010";
WHEN "111" => cr <="00010010";
END CASE;
ELSIF a<= "1111" THEN
CASE p IS
WHEN "000" => cr <="00000000";
WHEN "001" => cr <="00000000";
WHEN "010" => cr <="00000000";
WHEN "011" => cr <="00000000";
WHEN "100" => cr <="00000000";
WHEN "101" => cr <="00000011";
WHEN "110" => cr <="00000100";
WHEN "111" => cr <="00000100";
END CASE;
END IF;
END IF;
END IF;
END Process;
END s;
积分模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SCORE IS
PORT(ADD,CLK,RESET: IN STD_LOGIC;
SCOREOUT1,SCOREOUT2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END SCORE;
architecture s OF SCORE IS
SIGNAL SCR1,SCR2:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(ADD,CLK,RESET)
BEGIN
IF RESET = '1' THEN
SCR1<="0000";
SCR2<="0000";
ELSIF ADD'EVENT AND ADD='1' THEN
IF SCR1<"0111" THEN
IF SCR2 = "1001" THEN
SCR2 <= "0000";
SCR1 <= SCR1 + 1;
else
SCR2 <= SCR2 + 1;
END IF;
END IF;
END IF;
SCOREOUT1<=SCR1;
SCOREOUT2<=SCR2;
END PROCESS;
END architecture s;
计时模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TIME0 IS
PORT(CLK,RESET: IN STD_LOGIC;
TIMEOUT1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
TIMEOUT2:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
FIN:OUT STD_LOGIC);
END TIME0;
architecture s OF TIME0 IS
SIGNAL TIM1,TIM2:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK,RESET)
BEGIN
IF RESET = '1' THEN
TIM2<="0000";
TIM1<="0000";
ELSIF CLK'event AND CLK='1' AND RESET='0' THEN
FIN<='0' ;
IF TIM1<"0110" THEN
IF TIM2 = "1001" THEN
TIM2 <= "0000";
TIM1 <= TIM1 + 1;
ELSE
TIM2 <= TIM2 + 1;
END IF;
ELSE FIN<='1';
END IF;
END IF;
TIMEOUT1<=TIM1;
TIMEOUT2<=TIM2;
END PROCESS;
END architecture s;
数码管显示模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY YMG IS
PORT(CLK,RESET:IN STD_LOGIC;
SAO:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
T1,T2,S1,S2:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SEG,CAT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END YMG;
architecture s OF YMG IS
signal b,c:std_logic_vector(7 downto 0);
BEGIN
Process(RESET,CLK,T1,T2,S1,S2,SAO)
BEGIN
IF RESET = '1' THEN
SEG<="00000000";CAT <= "11111111";
ELSIF CLK'event AND CLK='1' THEN
IF SAO <= "00" THEN
c<="01111111";
CASE T1 IS
WHEN "0000" => b <= "11111110";
WHEN "0001" => b <= "10110000";
WHEN "0010" => b <= "11101101";
WHEN "0011" => b <= "11111001";
WHEN "0100" => b <= "10110011";
WHEN "0101" => b <= "11011011";
WHEN "0110" => b <= "11011111";
WHEN "0111" => b <= "11110000";
WHEN "1000" => b <= "11111111";
WHEN "1001" => b <= "11111011";
WHEN "1010" => b <= "11111110";
WHEN "1011" => b <= "10110000";
WHEN "1100" => b <= "11101101";
WHEN "1101" => b <= "11111001";
WHEN "1110" => b <= "10110011";
WHEN "1111" => b <= "11011011";
END CASE;
ELSIF SAO <= "01" THEN
c<="10111111";
CASE T2 IS
WHEN "0000" => b <= "11111110";
WHEN "0001" => b <= "10110000";
WHEN "0010" => b <= "11101101";
WHEN "0011" => b <= "11111001";
WHEN "0100" => b <= "10110011";
WHEN "0101" => b <= "11011011";
WHEN "0110" => b <= "11011111";
WHEN "0111" => b <= "11110000";
WHEN "1000" => b <= "11111111";
WHEN "1001" => b <= "11111011";
WHEN "1010" => b <= "11111110";
WHEN "1011" => b <= "10110000";
WHEN "1100" => b <= "11101101";
WHEN "1101" => b <= "11111001";
WHEN "1110" => b <= "10110011";
WHEN "1111" => b <= "11011011";
END CASE;
ELSIF SAO<="10" THEN
c<="11111101";
CASE S1 IS
WHEN "0000" => b <= "11111110";
WHEN "0001" => b <= "10110000";
WHEN "0010" => b <= "11101101";
WHEN "0011" => b <= "11111001";
WHEN "0100" => b <= "10110011";
WHEN "0101" => b <= "11011011";
WHEN "0110" => b <= "11011111";
WHEN "0111" => b <= "11110000";
WHEN "1000" => b <= "11111111";
WHEN "1001" => b <= "11111011";
WHEN "1010" => b <= "11111110";
WHEN "1011" => b <= "10110000";
WHEN "1100" => b <= "11101101";
WHEN "1101" => b <= "11111001";
WHEN "1110" => b <= "10110011";
WHEN "1111" => b <= "11011011";
END CASE;
ELSIF SAO<="11" THEN
c<="11111110";
CASE S2 IS
WHEN "0000" => b <= "11111110";
WHEN "0001" => b <= "10110000";
WHEN "0010" => b <= "11101101";
WHEN "0011" => b <= "11111001";
WHEN "0100" => b <= "10110011";
WHEN "0101" => b <= "11011011";
WHEN "0110" => b <= "11011111";
WHEN "0111" => b <= "11110000";
WHEN "1000" => b <= "11111111";
WHEN "1001" => b <= "11111011";
WHEN "1010" => b <= "11111110";
WHEN "1011" => b <= "10110000";
WHEN "1100" => b <= "11101101";
WHEN "1101" => b <= "11111001";
WHEN "1110" => b <= "10110011";
WHEN "1111" => b <= "11011011";
END CASE;
END IF;
SEG<=b;
CAT<=c;
END IF;
END Process;
END s;
秒分频器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BAIWAN IS
PORT(CLK:IN STD_LOGIC;
CLKOUT:OUT STD_LOGIC);
END BAIWAN;
ARCHITECTURE a OF BAIWAN IS
SIGNAL TMP: INTEGER RANGE 0 TO 9999999;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'event AND CLK='1' THEN
IF TMP<9999999 THEN
TMP <= TMP+1;
ELSE
TMP <= 0;
END IF;
IF tmp<4999999 THEN
CLKOUT <= '0';
ELSE
CLKOUT <= '1';
END IF;
END IF;
END PROCESS;
END a;
数码管扫描
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SM IS
PORT(CLK:IN STD_LOGIC;
CLK_OUT:OUT STD_LOGIC_VECTOR (1 DOWNTO 0));
END SM;
ARCHITECTURE a OF SM IS
BEGIN
PROCESS(clk)
VARIABLE TMP:STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN
IF CLK'EVENT AND CLK='1'
THEN
IF TMP="11" THEN TMP:="00";
ELSE TMP:=TMP+1;
END IF;
CLK_OUT <= TMP;
END IF;
END PROCESS;
END a;
发声模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity YY is
port(
clk : in std_logic;
reset : in std_logic;
voices: out std_logic
);
end YY;
architecture one of YY is
signal voices_temp : std_logic;
signal fen_div : std_logic_vector(15 downto 0);
begin
voices<=voices_temp;
process(clk,reset)
variable fen_out : std_logic_vector(15 downto 0);
variable cnt : integer range 0 to 15500;
begin
if reset='1' then
voices_temp<='0';
fen_out:=X"0000";
cnt:=0;
fen_div<=X"2552";
else
if rising_edge(clk) then
if fen_out = fen_div then
voices_temp<=not voices_temp;
fen_out:=X"0000";
cnt:=cnt+1;
if cnt = 500 then
fen_div<=X"2241";
elsif cnt = 1000 then
fen_div<=X"1D9F";
elsif cnt = 1500 then
fen_div<=X"2552";
elsif cnt = 2000 then
fen_div<=X"2552";
elsif cnt = 2500 then
fen_div<=X"2141";
elsif cnt = 3000 then
fen_div<=X"1D9F";
elsif cnt = 3500 then
fen_div<=X"2552";
elsif cnt = 4000 then
fen_div<=X"1D9F";
elsif cnt = 4500 then
fen_div<=X"1BF6";
elsif cnt = 5000 then
fen_div<=X"18E9";
elsif cnt = 6000 then
fen_div<=X"1D9F";
elsif cnt = 6500 then
fen_div<=X"1BF6";
elsif cnt = 6500 then
fen_div<=X"1BF6";
elsif cnt = 7000 then
fen_div<=X"18E9";
elsif cnt = 8000 then
fen_div<=X"18E9";
elsif cnt = 8250 then
fen_div<=X"1631";
elsif cnt = 8500 then
fen_div<=X"18E9";
elsif cnt = 8750 then
fen_div<=X"1D9F";
elsif cnt = 9000 then
fen_div<=X"1BF6";
elsif cnt = 9500 then
fen_div<=X"2552";
elsif cnt = 10000 then
fen_div<=X"18E9";
elsif cnt = 10250 then
fen_div<=X"1631";
elsif cnt = 10500 then
fen_div<=X"18E9";
elsif cnt = 10750 then
fen_div<=X"1BF6";
elsif cnt = 11250 then
fen_div<=X"1D9F";
elsif cnt = 11750 then
fen_div<=X"2552";
elsif cnt = 12250 then
fen_div<=X"2141";
elsif cnt = 12750 then
fen_div<=X"31D3";
elsif cnt = 13250 then
fen_div<=X"2552";
elsif cnt = 13750 then
fen_div<=X"2141";
elsif cnt = 14250 then
fen_div<=X"31D3";
elsif cnt = 14750 then
fen_div<=X"2552";
elsif cnt = 15000 then
cnt:=0;
fen_div<=X"2552";
end if;
else
fen_out:=fen_out+'1';
end if;
end if;
end if;
end process;
voices<=voices_temp;
end one;
最终输出模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FIN IS
PORT(F1,VV:IN STD_LOGIC;
DZZ:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
FVV:OUT STD_LOGIC;
FDZ:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END FIN;
ARCHITECTURE a OF FIN IS
BEGIN
PROCESS(F1,DZZ,VV)
BEGIN
IF F1='0' THEN
FDZ<=DZZ;
FVV<=VV;
ELSIF F1='1' THEN
FDZ<="11111111";
FVV<='0';
END IF;
END PROCESS;
END a;
- 功能说明及资源利用情况
功能说明：
本实验设计实现了以下功能：调节合适的输入频率，拨动重置开关后游戏开始，此时DISP1和DISP0显示得分“00”，DISP7和DISP6显示游戏时间“00”。
使用按键进入游戏状态，时间从00开始正计时，点阵在随机位置显示彩蛋，菜单颜色为红，每个彩蛋显示时间为1秒。在菜单显示时间内，按动相应位置按键表示击中彩蛋，得分增加并在彩蛋位置向四周扩散一圈，呈现爆炸效果。集中红蛋加1分，总得分显示在DISP1和DISP0。
游戏时间达到60s时游戏结束。
资源利用情况：
总工程：
- 故障及问题分析
本次实验中我主要遇到下列问题与难点
问题：判断不准确
原因：扫频不够高
解决方案：提高扫频频率
问题：计时无法停止
原因：未设定时间停止计时标识
解决方案：设置时间停止计时标识
问题：游戏结束时交互不完整
原因：没有设置游戏结束后如何显示
解决方案：设置最终显示模块，利用时间停止计时标识控制最终显示
- 总结和结论
在本次实验设计中，我先根据实验要求设计基本的总体框架，再向下细分模块，确定各模块的功能需求，依次编写和仿真调试各个模块的具体功能；然后在实体文件中将各模块元件化，整理map结构，编译总工程再不断调试，修改错误，调整代码细节；最后依次对照实验要求进行测试，使实验设计充分达到要求。
尽管实验设计与调试过程耗时很长，过程困难，且最后尚存一些不足之处，但我在过程中得到了很大收获。
首先我复习与巩固了quartus软件的使用，并具体掌握了分模块设计再整体连结完成总设计的方法，学到了很多quartus基本模块的写法，大致了解了状态机，信号与变量等概念的具体含义，了解了点阵发光，显示图像的基本原理等。具体掌握了vhdl语言的使用，并且对我学习数字电路课程有很大帮助。
其次我在设计过程中锻炼了自己的逻辑推理，与独立设计解决问题的能力，培养了我思考问题，分析问题的能力。
最后这次实验设计对我加强心理素质建设也有很大帮助，一次次编译不过和原理不理解常让我陷入困境，在不断面对困难解决困难的过程中，我的调节自身情绪，心态的能力得到了充分的锻炼，同时也让我明白理论知识与实际应用的差距，让我意识到实践对我掌握知识的必要性与巨大的推动作用。
北京邮电大学砸彩蛋大作业相关推荐
- 周杰伦新歌《说好不哭》彩蛋大汇总！ | 今日最佳
全世界只有3.14 % 的人关注了 青少年数学之旅 一首单曲,就霸占了一半的微博热搜榜,除了周杰伦,估计也没别人能做得到了. 回想起前段时间,周杰伦的中老年粉丝与ikun们围绕着"顶级流量& ...
- 计算机图形学大几学的,计算机图形学大作业-WenhaoYu.PDF
计算机图形学大作业-WenhaoYu 计算机图形学 大作业 5090379126 虞文豪 题目:通过光照及纹理映射,实现高度真实感青花瓷材质的 茶壶向茶杯倒水动画特效. 一． 概述 之前的作业用使用S ...
- android系统华为彩蛋,【小智】打开安卓“隐藏关卡”—— Android系统彩蛋大揭秘...
本帖最后由 丶浩南丶 于 2015-5-6 13:46 编辑 1354428994073.jpg (9.06 KB, 下载次数: 1) 2015-5-6 11:56 上传 "自从Andr ...
- python大作业80个_大黄蜂35个彩蛋解析！！你必看的80年代大风暴
Hello大家好,我是BA,变形金刚衍生作<大黄蜂>大家都到影院看了吗,觉得如何? 这次我为大家归纳了电影中出现的三十五个彩蛋,或者说是起发点,希望能够帮助大家更好的理解和认识电影的内在魅 ...
- short 类型的大小为( )个字节。_2008-2012，张一鸣在豆瓣书影音为字节跳动埋下的5个彩蛋...
2020年3月12号,字节跳动成立8周年之际,张一鸣在给全球员工的全员信中,宣布进行组织升级,以应对业务变化和组织成长的挑战. 回顾过去4年间张一鸣3次公开演讲(or全员信)和1次专访,可以看出,随着 ...
- HTML5期末大作业：漫画网站设计——海贼王基地(5页) 学生动漫网页设计模板下载 海贼王大学生HTML网页制作作品 简单漫画网页设计成品 dreamweaver学生网站模板
HTML5期末大作业:漫画网站设计--海贼王基地(5页) 学生动漫网页设计模板下载 海贼王大学生HTML网页制作作品 简单漫画网页设计成品 dreamweaver学生网站模板 常见网页设计作业题材有 ...
- android 微信表情雨,2017新年微信表情雨大召唤术-微信彩蛋表情雨2017预约 _5577安卓网...
迎接鸡年,微信也更新了至少4个彩蛋,微信方面还透露,春节期间,大家还可以定制新春表情包,棒棒哒!微信表情雨2017有效,2017微信下雨口令大全,2017微信聊天下雨口令,微信下雨口令大全,微信表情雨 ...
- B1HTML5期末大作业：动漫网站设计——海贼王中乔巴漫画(5页) 学生动漫网页设计模板下载 海贼王大学生HTML网页制作作品 简单漫画网页设计成品 dreamweaver学生网站模板
HTML5期末大作业:动漫网站设计--海贼王中乔巴漫画(5页) 学生动漫网页设计模板下载 海贼王大学生HTML网页制作作品 简单漫画网页设计成品 dreamweaver学生网站模板 常见网页设计作业题 ...
- HTML5期末大作业：动漫网站设计——斗破苍穹动漫(6页) HTML+CSS+JavaScript 学生动漫网页设计模板下载 斗破大学生HTML网页制作作品 简单漫画网页设计成品 dreamweav
HTML5期末大作业:动漫网站设计--斗破苍穹动漫(6页) HTML+CSS+JavaScript 学生动漫网页设计模板下载 斗破大学生HTML网页制作作品 简单漫画网页设计成品 dreamweave ...
- 给你惊喜！来看看国内大公司官网隐藏的彩蛋
热文导读| 点击标题阅读 金九银十跳槽季如何进阶找到合适满意的工作? 华为员工论坛炫耀:工作16年,就挣了一套1400万的房 那些一毕业就选择华为的人,后来都怎么样了 百度 爱奇艺 知乎 天猫 京东 ...
最新文章
- android 无法接收广播_别告诉我你不认识Android中广播接收者（二）
- 【转】提高PHP性能的53个技巧
- EDM邮件营销之如何制作模板
- win7小工具打不开_Win7系统电脑桌面双击快捷键方式图标没反应的解决办法
- 通向架构师的道路（第八天）之weblogic与apache的整合与调优 转
- 三极管基极限流电阻计算
- 【最后一天报名】数据科学峰会分论坛：供应链、用户增长、电商零售
- 三重积分(Triple Integral)
- python如何定义函数k_Python 函数
- Fusion 360 常见问题
- 克里金插值---MATLAB程序
- oracle触发器如何调试
- 志翔亮相中国网络安全年会 终端安全要“轻管控，重感知”
- 基于stm32的模拟楼道光控开关的实验
- Android虚拟键盘的高度计算
- 零基础学Python：Matplotlib用法
- 机房收费系统 项目总结
- mysee的零散，方便以后汇总
- Sql Server Md5使用
- vueRouter history模式和hash模式的区别
热门文章
- PLSQL的快捷键以及使用技巧
- 如何自学CAD制图？学会这5个方法，只需一周就能从小白变大神
- IOS Websocket (一) Starscream实现Websocket通讯
- Microsoft Designer 微软设计师 拆机（拆鼠标）路程
- Solana沦为“宕机链”：TPS修正主义的又一次失败
- OutMan——Foundation框架中的集合类（一）（二）
- 惠普笔记本电脑重装系统后找不到引导设备
- Unity小游戏算法分析与实现（Unity+XR+游戏开发+算法+MVC+斗地主+耳轮跳+见缝插针+王者荣耀+绝地求生+立钻哥哥+==）
- 刷百度权重那些不为人知的事情
- java is alphabetic_\p{IsAlphabetic}