Keil5 平台 S3C2440裸机程序开发-----中断系统/UART
2024-05-16 00:12:59
目录
前言
一、启动文件
二、代码
main.c
uart.c
uart.h
led.c
led.h
S3C2440.h
三、编译，烧录，打开串口助手，接收到数据。
前言
本博文介绍mini2440开发板,在keil5平台上进行裸机开发中关于中断系统及串口中断的一些配置。
一、启动文件
参考文档
S3C2440的Keil启动文件S3C2440.s添加中断配置
keil自带的启动文件S3C2440.s没有中断配置的，需要自行添加中断配置。
;/*****************************************************************************/
;/* S3C2440.S: Startup file for Samsung S3C440 */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>> */
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools. */
;/* Copyright (c) 2005-2008 Keil Software. All rights reserved. */
;/* This software may only be used under the terms of a valid, current, */
;/* end user licence from KEIL for a compatible version of KEIL software */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/;/*
; * The S3C2440.S code is executed after CPU Reset. This file may be
; * translated with the following SET symbols. In uVision these SET
; * symbols are entered under Options - ASM - Define.
; *
; * NO_CLOCK_SETUP: when set the startup code will not initialize Clock
; * (used mostly when clock is already initialized from script .ini
; * file).
; *
; * NO_MC_SETUP: when set the startup code will not initialize Memory
; * Controller (used mostly when clock is already initialized from script
; * .ini file).
; *
; * NO_GP_SETUP: when set the startup code will not initialize General Ports
; * (used mostly when clock is already initialized from script .ini
; * file).
; *
; * RAM_INTVEC: when set the startup code copies exception vectors
; * from execution address to on-chip RAM.
; */;=================
; INTERRUPT
;=================
SRCPND EQU 0x4a000000 ;Interrupt request status
INTMOD EQU 0x4a000004 ;Interrupt mode control
INTMSK EQU 0x4a000008 ;Interrupt mask control
PRIORITY EQU 0x4a00000c ;IRQ priority control <-- May 06, 2002 SOP
INTPND EQU 0x4a000010 ;Interrupt request status
INTOFFSET EQU 0x4a000014 ;Interruot request source offset
SUSSRCPND EQU 0x4a000018 ;Sub source pending
INTSUBMSK EQU 0x4a00001c ;Interrupt sub mask
_ISR_STARTADDRESS EQU 0x33ffff00; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRsMode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1FI_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled;----------------------- Stack and Heap Definitions ----------------------------;// <h> Stack Configuration (Stack Sizes in Bytes)
;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
;// </h>UND_Stack_Size EQU 0x00000000
SVC_Stack_Size EQU 0x00000008
ABT_Stack_Size EQU 0x00000000
FIQ_Stack_Size EQU 0x00000000
IRQ_Stack_Size EQU 0x00000080
USR_Stack_Size EQU 0x00000400ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \FIQ_Stack_Size + IRQ_Stack_Size)AREA STACK, NOINIT, READWRITE, ALIGN=3Stack_Mem SPACE USR_Stack_Size
__initial_sp SPACE ISR_Stack_Size
Stack_Top;// <h> Heap Configuration
;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>Heap_Size EQU 0x00000000AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit;----------------------- Memory Definitions ------------------------------------; Internal Memory Base Addresses
IRAM_BASE EQU 0x40000000;----------------------- Watchdog Timer Definitions ----------------------------WT_BASE EQU 0x53000000 ; Watchdog Timer Base Address
WTCON_OFS EQU 0x00 ; Watchdog Timer Control Register Offset
WTDAT_OFS EQU 0x04 ; Watchdog Timer Data Register Offset
WTCNT_OFS EQU 0x08 ; Watchdog Timer Count Register Offset;// <e> Watchdog Timer Setup
;// <h> Watchdog Timer Control Register (WTCON)
;// <o1.8..15> Prescaler Value <0-255>
;// <o1.5> Watchdog Timer Enable
;// <o1.3..4> Clock Division Factor
;// <0=> 16 <1=> 32 <2=> 64 <3=> 128
;// <o1.2> Interrupt Generation Enable
;// <o1.0> Reset Enable
;// </h>
;// <h> Watchdog Timer Data Register (WTDAT)
;// <o2.0..15> Count Reload Value <0-65535>
;// </h>
;// </e> Watchdog Timer Setup
WT_SETUP EQU 1
WTCON_Val EQU 0x00000000
WTDAT_Val EQU 0x00008000;----------------------- Clock and Power Management Definitions ----------------CLOCK_BASE EQU 0x4C000000 ; Clock Base Address
LOCKTIME_OFS EQU 0x00 ; PLL Lock Time Count Register Offset
MPLLCON_OFS EQU 0x04 ; MPLL Configuration Register Offset
UPLLCON_OFS EQU 0x08 ; UPLL Configuration Register Offset
CLKCON_OFS EQU 0x0C ; Clock Generator Control Reg Offset
CLKSLOW_OFS EQU 0x10 ; Clock Slow Control Register Offset
CLKDIVN_OFS EQU 0x14 ; Clock Divider Control Register Offset
CAMDIVN_OFS EQU 0x18 ; Camera Clock Divider Register Offset;// <e> Clock Setup
;// <h> PLL Lock Time Count Register (LOCKTIME)
;// <o1.16..31> U_LTIME: UPLL Lock Time Count Value for UCLK <0x0-0xFFFF>
;// <o1.0..15> M_LTIME: MPLL Lock Time Count Value for FCLK, HCLK and PCLK <0x0-0xFFFF>
;// </h>
;// <h> MPLL Configuration Register (MPLLCON)
;// <i> MPLL = (2 * m * Fin) / (p * 2^s)
;// <o2.12..19> m: Main Divider m Value <9-256><#-8>
;// <i> m = MDIV + 8
;// <o2.4..9> p: Pre-divider p Value <3-64><#-2>
;// <i> p = PDIV + 2
;// <o2.0..1> s: Post Divider s Value <0-3>
;// <i> s = SDIV
;// </h>
;// <h> UPLL Configuration Register (UPLLCON)
;// <i> UPLL = ( m * Fin) / (p * 2^s)
;// <o3.12..19> m: Main Divider m Value <8-263><#-8>
;// <i> m = MDIV + 8
;// <o3.4..9> p: Pre-divider p Value <2-65><#-2>
;// <i> p = PDIV + 2
;// <o3.0..1> s: Post Divider s Value <0-3>
;// <i> s = SDIV
;// </h>
;// <h> Clock Generation Control Register (CLKCON)
;// <o4.20> AC97 Enable
;// <o4.19> Camera Enable
;// <o4.18> SPI Enable
;// <o4.17> IIS Enable
;// <o4.16> IIC Enable
;// <o4.15> ADC + Touch Screen Enable
;// <o4.14> RTC Enable
;// <o4.13> GPIO Enable
;// <o4.12> UART2 Enable
;// <o4.11> UART1 Enable
;// <o4.10> UART0 Enable
;// <o4.9> SDI Enable
;// <o4.8> PWMTIMER Enable
;// <o4.7> USB Device Enable
;// <o4.6> USB Host Enable
;// <o4.5> LCDC Enable
;// <o4.4> NAND FLASH Controller Enable
;// <o4.3> SLEEP Enable
;// <o4.2> IDLE BIT Enable
;// </h>
;// <h> Clock Slow Control Register (CLKSLOW)
;// <o5.7> UCLK_ON: UCLK ON
;// <o5.5> MPLL_OFF: Turn off PLL
;// <o5.4> SLOW_BIT: Slow Mode Enable
;// <o5.0..2> SLOW_VAL: Slow Clock Divider <0-7>
;// </h>
;// <h> Clock Divider Control Register (CLKDIVN)
;// <o6.3> DIVN_UPLL: UCLK Select
;// <0=> UCLK = UPLL clock
;// <1=> UCLK = UPLL clock / 2
;// <o6.1..2> HDIVN: HCLK Select
;// <0=> HCLK = FCLK
;// <1=> HCLK = FCLK / 2
;// <2=> HCLK = FCLK / 4 if HCLK4_HALF = 0 in CAMDIVN, else HCLK = FCLK / 8
;// <3=> HCLK = FCLK / 3 if HCLK3_HALF = 0 in CAMDIVN, else HCLK = FCLK / 6
;// <o6.0> PDIVN: PCLK Select
;// <0=> PCLK = HCLK
;// <1=> PCLK = HCLK / 2
;// </h>
;// <h> Camera Clock Divider Control Register (CAMDIVN)
;// <o7.12> DVS_EN: ARM Core Clock Select
;// <0=> ARM core runs at FCLK
;// <1=> ARM core runs at HCLK
;// <o7.9> HCLK4_HALF: HDIVN Division Rate Change Bit
;// <0=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 4
;// <1=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 8
;// <o7.8> HCLK3_HALF: HDIVN Division Rate Change Bit
;// <0=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 3
;// <1=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 6
;// <o7.4> CAMCLK Select
;// <0=> CAMCLK = UPLL
;// <1=> CAMCLK = UPLL / CAMCLK_DIV
;// <o7.0..3> CAMCLK_DIV: CAMCLK Divider <0-15>
;// <i> Camera Clock = UPLL / (2 * (CAMCLK_DIV + 1))
;// <i> Divider is used only if CAMCLK_SEL = 1
;// </h>
;// </e> Clock Setup
CLOCK_SETUP EQU 1
LOCKTIME_Val EQU 0x0FFF0FFF
MPLLCON_Val EQU 0x00043011
UPLLCON_Val EQU 0x00038021
CLKCON_Val EQU 0x001FFFF0
CLKSLOW_Val EQU 0x00000004
CLKDIVN_Val EQU 0x0000000F
CAMDIVN_Val EQU 0x00000000;----------------------- Memory Controller Definitions -------------------------MC_BASE EQU 0x48000000 ; Memory Controller Base Address
BWSCON_OFS EQU 0x00 ; Bus Width and Wait Status Ctrl Offset
BANKCON0_OFS EQU 0x04 ; Bank 0 Control Register Offset
BANKCON1_OFS EQU 0x08 ; Bank 1 Control Register Offset
BANKCON2_OFS EQU 0x0C ; Bank 2 Control Register Offset
BANKCON3_OFS EQU 0x10 ; Bank 3 Control Register Offset
BANKCON4_OFS EQU 0x14 ; Bank 4 Control Register Offset
BANKCON5_OFS EQU 0x18 ; Bank 5 Control Register Offset
BANKCON6_OFS EQU 0x1C ; Bank 6 Control Register Offset
BANKCON7_OFS EQU 0x20 ; Bank 7 Control Register Offset
REFRESH_OFS EQU 0x24 ; SDRAM Refresh Control Register Offset
BANKSIZE_OFS EQU 0x28 ; Flexible Bank Size Register Offset
MRSRB6_OFS EQU 0x2C ; Bank 6 Mode Register Offset
MRSRB7_OFS EQU 0x30 ; Bank 7 Mode Register Offset;// <e> Memory Controller Setup
;// <h> Bus Width and Wait Control Register (BWSCON)
;// <o1.31> ST7: Use UB/LB for Bank 7
;// <o1.30> WS7: Enable Wait Status for Bank 7
;// <o1.28..29> DW7: Data Bus Width for Bank 7
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
;// <o1.27> ST6: Use UB/LB for Bank 6
;// <o1.26> WS6: Enable Wait Status for Bank 6
;// <o1.24..25> DW6: Data Bus Width for Bank 6
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
;// <o1.23> ST5: Use UB/LB for Bank 5
;// <o1.22> WS5: Enable Wait Status for Bank 5
;// <o1.20..21> DW5: Data Bus Width for Bank 5
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
;// <o1.19> ST4: Use UB/LB for Bank 4
;// <o1.18> WS4: Enable Wait Status for Bank 4
;// <o1.16..17> DW4: Data Bus Width for Bank 4
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
;// <o1.15> ST3: Use UB/LB for Bank 3
;// <o1.14> WS3: Enable Wait Status for Bank 3
;// <o1.12..13> DW3: Data Bus Width for Bank 3
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
;// <o1.11> ST2: Use UB/LB for Bank 2
;// <o1.10> WS2: Enable Wait Status for Bank 2
;// <o1.8..9> DW2: Data Bus Width for Bank 2
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
;// <o1.7> ST1: Use UB/LB for Bank 1
;// <o1.6> WS1: Enable Wait Status for Bank 1
;// <o1.4..5> DW1: Data Bus Width for Bank 1
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
;// <o1.1..2> DW0: Indicate Data Bus Width for Bank 0
;// <1=> 16-bit <2=> 32-bit
;// </h>
;// <h> Bank 0 Control Register (BANKCON0)
;// <o2.13..14> Tacs: Address Set-up Time before nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o2.11..12> Tcos: Chip Selection Set-up Time before nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o2.8..10> Tacc: Access Cycle
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
;// <o2.6..7> Tcoh: Chip Selection Hold Time after nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o2.4..5> Tcah: Address Hold Time after nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o2.2..3> Tacp: Page Mode Access Cycle at Page Mode
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
;// <o2.0..1> PMC: Page Mode Configuration
;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
;// </h>
;// <h> Bank 1 Control Register (BANKCON1)
;// <o3.13..14> Tacs: Address Set-up Time before nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o3.11..12> Tcos: Chip Selection Set-up Time before nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o3.8..10> Tacc: Access Cycle
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
;// <o3.6..7> Tcoh: Chip Selection Hold Time after nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o3.4..5> Tcah: Address Hold Time after nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o3.2..3> Tacp: Page Mode Access Cycle at Page Mode
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
;// <o3.0..1> PMC: Page Mode Configuration
;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
;// </h>
;// <h> Bank 2 Control Register (BANKCON2)
;// <o4.13..14> Tacs: Address Set-up Time before nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o4.11..12> Tcos: Chip Selection Set-up Time before nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o4.8..10> Tacc: Access Cycle
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
;// <o4.6..7> Tcoh: Chip Selection Hold Time after nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o4.4..5> Tcah: Address Hold Time after nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o4.2..3> Tacp: Page Mode Access Cycle at Page Mode
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
;// <o4.0..1> PMC: Page Mode Configuration
;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
;// </h>
;// <h> Bank 3 Control Register (BANKCON3)
;// <o5.13..14> Tacs: Address Set-up Time before nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o5.11..12> Tcos: Chip Selection Set-up Time before nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o5.8..10> Tacc: Access Cycle
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
;// <o5.6..7> Tcoh: Chip Selection Hold Time after nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o5.4..5> Tcah: Address Hold Time after nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o5.2..3> Tacp: Page Mode Access Cycle at Page Mode
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
;// <o5.0..1> PMC: Page Mode Configuration
;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
;// </h>
;// <h> Bank 4 Control Register (BANKCON4)
;// <o6.13..14> Tacs: Address Set-up Time before nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o6.11..12> Tcos: Chip Selection Set-up Time before nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o6.8..10> Tacc: Access Cycle
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
;// <o6.6..7> Tcoh: Chip Selection Hold Time after nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o6.4..5> Tcah: Address Hold Time after nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o6.2..3> Tacp: Page Mode Access Cycle at Page Mode
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
;// <o6.0..1> PMC: Page Mode Configuration
;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
;// </h>
;// <h> Bank 5 Control Register (BANKCON5)
;// <o7.13..14> Tacs: Address Set-up Time before nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o7.11..12> Tcos: Chip Selection Set-up Time before nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o7.8..10> Tacc: Access Cycle
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
;// <o7.6..7> Tcoh: Chip Selection Hold Time after nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o7.4..5> Tcah: Address Hold Time after nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o7.2..3> Tacp: Page Mode Access Cycle at Page Mode
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
;// <o7.0..1> PMC: Page Mode Configuration
;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
;// </h>
;// <h> Bank 6 Control Register (BANKCON6)
;// <o8.15..16> Memory Type Selection
;// <0=> ROM or SRAM <3=> SDRAM
;// <o8.13..14> Tacs: Address Set-up Time before nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o8.11..12> Tcos: Chip Selection Set-up Time before nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o8.8..10> Tacc: Access Cycle
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
;// <o8.6..7> Tcoh: Chip Selection Hold Time after nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o8.4..5> Tcah: Address Hold Time after nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o8.2..3> Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay
;// <i> Parameter depends on Memory Type: if type SRAM then parameter is Tacp,
;// <i> if type is SDRAM then parameter is Trcd
;// <i> For SDRAM 6 cycles setting is not allowed
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
;// <o8.0..1> PMC/SCAN: Page Mode Configuration / Column Address Number <0-3>
;// <i> Parameter depends on Memory Type: if type SRAM then parameter is PMC,
;// <i> if type is SDRAM then parameter is SCAN
;// </h>
;// <h> Bank 7 Control Register (BANKCON7)
;// <o9.15..16> Memory Type Selection
;// <0=> ROM or SRAM <3=> SDRAM
;// <o9.13..14> Tacs: Address Set-up Time before nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o9.11..12> Tcos: Chip Selection Set-up Time before nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o9.8..10> Tacc: Access Cycle
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
;// <o9.6..7> Tcoh: Chip Selection Hold Time after nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o9.4..5> Tcah: Address Hold Time after nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o9.2..3> Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay
;// <i> Parameter depends on Memory Type: if type SRAM then parameter is Tacp,
;// <i> if type is SDRAM then parameter is Trcd
;// <i> For SDRAM 6 cycles setting is not allowed
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
;// <o9.0..1> PMC/SCAN: Page Mode Configuration / Column Address Number <0-3>
;// <i> Parameter depends on Memory Type: if type SRAM then parameter is PMC,
;// <i> if type is SDRAM then parameter is SCAN
;// </h>
;// <h> SDRAM Refresh Control Register (REFRESH)
;// <o10.23> REFEN: SDRAM Refresh Enable
;// <o10.22> TREFMD: SDRAM Refresh Mode
;// <0=> CBR/Auto Refresh <1=> Self Refresh
;// <o10.20..21> Trp: SDRAM RAS Pre-charge Time
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> Reserved
;// <o10.18..19> Tsrc: SDRAM Semi Row Cycle Time
;// <i> SDRAM Row cycle time: Trc = Tsrc + Trp
;// <0=> 4 clocks <1=> 5 clocks <2=> 6 clocks <3=> 7 clocks
;// <o10.0..10> Refresh Counter <0-1023>
;// <i> Refresh Period = (2048 - Refresh Count + 1) / HCLK
;// </h>
;// <h> Flexible Bank Size Register (BANKSIZE)
;// <o11.7> BURST_EN: ARM Core Burst Operation Enable
;// <o11.5> SCKE_EN: SDRAM Power Down Mode Enable
;// <o11.4> SCLK_EN: SCLK Enabled During SDRAM Access Cycle
;// <0=> SCLK is always active <1=> SCLK is active only during the access
;// <o11.0..2> BK76MAP: BANK6 and BANK7 Memory Map
;// <0=> 32MB / 32MB <1=> 64MB / 64MB <2=> 128MB / 128MB
;// <4=> 2MB / 2MB <5=> 4MB / 4MB <6=> 8MB / 8MB <7=> 16MB / 16MB
;// <o11.0..10> Refresh Counter <0-1023>
;// <i> Refresh Period = (2048 - Refresh Count + 1) / HCLK
;// </h>
;// <h> SDRAM Mode Register Set Register 6 (MRSRB6)
;// <o12.7> WBL: Write Burst Length
;// <0=> Burst (Fixed)
;// <o12.7..8> TM: Test Mode
;// <0=> Mode register set (Fixed)
;// <o12.4..6> CL: CAS Latency
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks
;// <o12.3> BT: Burst Type
;// <0=> Sequential (Fixed)
;// <o12.0..2> BL: Burst Length
;// <0=> 1 (Fixed)
;// </h>
;// <h> SDRAM Mode Register Set Register 7 (MRSRB7)
;// <o13.7> WBL: Write Burst Length
;// <0=> Burst (Fixed)
;// <o13.7..8> TM: Test Mode
;// <0=> Mode register set (Fixed)
;// <o13.4..6> CL: CAS Latency
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks
;// <o13.3> BT: Burst Type
;// <0=> Sequential (Fixed)
;// <o13.0..2> BL: Burst Length
;// <0=> 1 (Fixed)
;// </h>
;// </e> Memory Controller Setup
MC_SETUP EQU 1
BWSCON_Val EQU 0x22000000
BANKCON0_Val EQU 0x00000700
BANKCON1_Val EQU 0x00000700
BANKCON2_Val EQU 0x00000700
BANKCON3_Val EQU 0x00000700
BANKCON4_Val EQU 0x00000700
BANKCON5_Val EQU 0x00000700
BANKCON6_Val EQU 0x00018005
BANKCON7_Val EQU 0x00018005
REFRESH_Val EQU 0x008404F3
BANKSIZE_Val EQU 0x00000032
MRSRB6_Val EQU 0x00000020
MRSRB7_Val EQU 0x00000020;----------------------- I/O Port Definitions ----------------------------------GPA_BASE EQU 0x56000000 ; GPA Base Address
GPB_BASE EQU 0x56000010 ; GPB Base Address
GPC_BASE EQU 0x56000020 ; GPC Base Address
GPD_BASE EQU 0x56000030 ; GPD Base Address
GPE_BASE EQU 0x56000040 ; GPE Base Address
GPF_BASE EQU 0x56000050 ; GPF Base Address
GPG_BASE EQU 0x56000060 ; GPG Base Address
GPH_BASE EQU 0x56000070 ; GPH Base Address
GPJ_BASE EQU 0x560000D0 ; GPJ Base Address
GPCON_OFS EQU 0x00 ; Control Register Offset
GPDAT_OFS EQU 0x04 ; Data Register Offset
GPUP_OFS EQU 0x08 ; Pull-up Disable Register Offset;// <e> I/O Setup
GP_SETUP EQU 1;// <e> Port A Settings
;// <h> Port A Control Register (GPACON)
;// <o1.22> GPA22 <0=> Output <1=> nFCE
;// <o1.21> GPA21 <0=> Output <1=> nRSTOUT
;// <o1.20> GPA20 <0=> Output <1=> nFRE
;// <o1.19> GPA19 <0=> Output <1=> nFWE
;// <o1.18> GPA18 <0=> Output <1=> ALE
;// <o1.17> GPA17 <0=> Output <1=> CLE
;// <o1.16> GPA16 <0=> Output <1=> nGCS[5]
;// <o1.15> GPA15 <0=> Output <1=> nGCS[4]
;// <o1.14> GPA14 <0=> Output <1=> nGCS[3]
;// <o1.13> GPA13 <0=> Output <1=> nGCS[2]
;// <o1.12> GPA12 <0=> Output <1=> nGCS[1]
;// <o1.11> GPA11 <0=> Output <1=> ADDR26
;// <o1.10> GPA10 <0=> Output <1=> ADDR25
;// <o1.9> GPA9 <0=> Output <1=> ADDR24
;// <o1.8> GPA8 <0=> Output <1=> ADDR23
;// <o1.7> GPA7 <0=> Output <1=> ADDR22
;// <o1.6> GPA6 <0=> Output <1=> ADDR21
;// <o1.5> GPA5 <0=> Output <1=> ADDR20
;// <o1.4> GPA4 <0=> Output <1=> ADDR19
;// <o1.3> GPA3 <0=> Output <1=> ADDR18
;// <o1.2> GPA2 <0=> Output <1=> ADDR17
;// <o1.1> GPA1 <0=> Output <1=> ADDR16
;// <o1.0> GPA0 <0=> Output <1=> ADDR0
;// </h>
;// </e>
GPA_SETUP EQU 0
GPACON_Val EQU 0x000003FF;// <e> Port B Settings
;// <h> Port B Control Register (GPBCON)
;// <o1.20..21> GPB10 <0=> Input <1=> Output <2=> nXDREQ0 <3=> Reserved
;// <o1.18..19> GPB9 <0=> Input <1=> Output <2=> nXDACK0 <3=> Reserved
;// <o1.16..17> GPB8 <0=> Input <1=> Output <2=> nXDREQ1 <3=> Reserved
;// <o1.14..15> GPB7 <0=> Input <1=> Output <2=> nXDACK1 <3=> Reserved
;// <o1.12..13> GPB6 <0=> Input <1=> Output <2=> nXBREQ <3=> Reserved
;// <o1.10..11> GPB5 <0=> Input <1=> Output <2=> nXBACK <3=> Reserved
;// <o1.8..9> GPB4 <0=> Input <1=> Output <2=> TCLK[0] <3=> Reserved
;// <o1.6..7> GPB3 <0=> Input <1=> Output <2=> TOUT3 <3=> Reserved
;// <o1.4..5> GPB2 <0=> Input <1=> Output <2=> TOUT2 <3=> Reserved
;// <o1.2..3> GPB1 <0=> Input <1=> Output <2=> TOUT1 <3=> Reserved
;// <o1.0..1> GPB0 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved
;// </h>
;// <h> Port B Pull-up Settings Register (GPBUP)
;// <o2.10> GPB10 Pull-up Disable
;// <o2.9> GPB9 Pull-up Disable
;// <o2.8> GPB8 Pull-up Disable
;// <o2.7> GPB7 Pull-up Disable
;// <o2.6> GPB6 Pull-up Disable
;// <o2.5> GPB5 Pull-up Disable
;// <o2.4> GPB4 Pull-up Disable
;// <o2.3> GPB3 Pull-up Disable
;// <o2.2> GPB2 Pull-up Disable
;// <o2.1> GPB1 Pull-up Disable
;// <o2.0> GPB0 Pull-up Disable
;// </h>
;// </e>
GPB_SETUP EQU 0
GPBCON_Val EQU 0x00000000
GPBUP_Val EQU 0x00000000 ;// <e> Port C Settings
;// <h> Port C Control Register (GPCCON)
;// <o1.30..31> GPC15 <0=> Input <1=> Output <2=> VD[7] <3=> Reserved
;// <o1.28..29> GPC14 <0=> Input <1=> Output <2=> VD[6] <3=> Reserved
;// <o1.26..27> GPC13 <0=> Input <1=> Output <2=> VD[5] <3=> Reserved
;// <o1.24..25> GPC12 <0=> Input <1=> Output <2=> VD[4] <3=> Reserved
;// <o1.22..23> GPC11 <0=> Input <1=> Output <2=> VD[3] <3=> Reserved
;// <o1.20..21> GPC10 <0=> Input <1=> Output <2=> VD[2] <3=> Reserved
;// <o1.18..19> GPC9 <0=> Input <1=> Output <2=> VD[1] <3=> Reserved
;// <o1.16..17> GPC8 <0=> Input <1=> Output <2=> VD[0] <3=> Reserved
;// <o1.14..15> GPC7 <0=> Input <1=> Output <2=> LCD_LPCREVB <3=> Reserved
;// <o1.12..13> GPC6 <0=> Input <1=> Output <2=> LCD_LPCREV <3=> Reserved
;// <o1.10..11> GPC5 <0=> Input <1=> Output <2=> LCD_LPCOE <3=> Reserved
;// <o1.8..9> GPC4 <0=> Input <1=> Output <2=> VM <3=> I2SSDI
;// <o1.6..7> GPC3 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved
;// <o1.4..5> GPC2 <0=> Input <1=> Output <2=> VLINE <3=> Reserved
;// <o1.2..3> GPC1 <0=> Input <1=> Output <2=> VCLK <3=> Reserved
;// <o1.0..1> GPC0 <0=> Input <1=> Output <2=> LEND <3=> Reserved
;// </h>
;// <h> Port C Pull-up Settings Register (GPCUP)
;// <o2.15> GPC15 Pull-up Disable
;// <o2.14> GPC14 Pull-up Disable
;// <o2.13> GPC13 Pull-up Disable
;// <o2.12> GPC12 Pull-up Disable
;// <o2.11> GPC11 Pull-up Disable
;// <o2.10> GPC10 Pull-up Disable
;// <o2.9> GPC9 Pull-up Disable
;// <o2.8> GPC8 Pull-up Disable
;// <o2.7> GPC7 Pull-up Disable
;// <o2.6> GPC6 Pull-up Disable
;// <o2.5> GPC5 Pull-up Disable
;// <o2.4> GPC4 Pull-up Disable
;// <o2.3> GPC3 Pull-up Disable
;// <o2.2> GPC2 Pull-up Disable
;// <o2.1> GPC1 Pull-up Disable
;// <o2.0> GPC0 Pull-up Disable
;// </h>
;// </e>
GPC_SETUP EQU 0
GPCCON_Val EQU 0x00000000
GPCUP_Val EQU 0x00000000;// <e> Port D Settings
;// <h> Port D Control Register (GPDCON)
;// <o1.30..31> GPD15 <0=> Input <1=> Output <2=> VD[23] <3=> nSS0
;// <o1.28..29> GPD14 <0=> Input <1=> Output <2=> VD[22] <3=> nSS1
;// <o1.26..27> GPD13 <0=> Input <1=> Output <2=> VD[21] <3=> Reserved
;// <o1.24..25> GPD12 <0=> Input <1=> Output <2=> VD[20] <3=> Reserved
;// <o1.22..23> GPD11 <0=> Input <1=> Output <2=> VD[19] <3=> Reserved
;// <o1.20..21> GPD10 <0=> Input <1=> Output <2=> VD[18] <3=> SPICLK1
;// <o1.18..19> GPD9 <0=> Input <1=> Output <2=> VD[17] <3=> SPIMOSI1
;// <o1.16..17> GPD8 <0=> Input <1=> Output <2=> VD[16] <3=> SPIMISO1
;// <o1.14..15> GPD7 <0=> Input <1=> Output <2=> VD[15] <3=> Reserved
;// <o1.12..13> GPD6 <0=> Input <1=> Output <2=> VD[14] <3=> Reserved
;// <o1.10..11> GPD5 <0=> Input <1=> Output <2=> VD[13] <3=> Reserved
;// <o1.8..9> GPD4 <0=> Input <1=> Output <2=> VD[12] <3=> Reserved
;// <o1.6..7> GPD3 <0=> Input <1=> Output <2=> VD[11] <3=> Reserved
;// <o1.4..5> GPD2 <0=> Input <1=> Output <2=> VD[10] <3=> Reserved
;// <o1.2..3> GPD1 <0=> Input <1=> Output <2=> VD[9] <3=> Reserved
;// <o1.0..1> GPD0 <0=> Input <1=> Output <2=> VD[8] <3=> Reserved
;// </h>
;// <h> Port D Pull-up Settings Register (GPDUP)
;// <o2.15> GPD15 Pull-up Disable
;// <o2.14> GPD14 Pull-up Disable
;// <o2.13> GPD13 Pull-up Disable
;// <o2.12> GPD12 Pull-up Disable
;// <o2.11> GPD11 Pull-up Disable
;// <o2.10> GPD10 Pull-up Disable
;// <o2.9> GPD9 Pull-up Disable
;// <o2.8> GPD8 Pull-up Disable
;// <o2.7> GPD7 Pull-up Disable
;// <o2.6> GPD6 Pull-up Disable
;// <o2.5> GPD5 Pull-up Disable
;// <o2.4> GPD4 Pull-up Disable
;// <o2.3> GPD3 Pull-up Disable
;// <o2.2> GPD2 Pull-up Disable
;// <o2.1> GPD1 Pull-up Disable
;// <o2.0> GPD0 Pull-up Disable
;// </h>
;// </e>
GPD_SETUP EQU 0
GPDCON_Val EQU 0x00000000
GPDUP_Val EQU 0x00000000;// <e> Port E Settings
;// <h> Port E Control Register (GPECON)
;// <o1.30..31> GPE15 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved
;// <i> This pad is open-drain, and has no pull-up option.
;// <o1.28..29> GPE14 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved
;// <i> This pad is open-drain, and has no pull-up option.
;// <o1.26..27> GPE13 <0=> Input <1=> Output <2=> SPICLK0 <3=> Reserved
;// <o1.24..25> GPE12 <0=> Input <1=> Output <2=> SPIMOSI0 <3=> Reserved
;// <o1.22..23> GPE11 <0=> Input <1=> Output <2=> SPIMISO0 <3=> Reserved
;// <o1.20..21> GPE10 <0=> Input <1=> Output <2=> SDDAT3 <3=> Reserved
;// <o1.18..19> GPE9 <0=> Input <1=> Output <2=> SDDAT2 <3=> Reserved
;// <o1.16..17> GPE8 <0=> Input <1=> Output <2=> SDDAT1 <3=> Reserved
;// <o1.14..15> GPE7 <0=> Input <1=> Output <2=> SDDAT0 <3=> Reserved
;// <o1.12..13> GPE6 <0=> Input <1=> Output <2=> SDCMD <3=> Reserved
;// <o1.10..11> GPE5 <0=> Input <1=> Output <2=> SDCLK <3=> Reserved
;// <o1.8..9> GPE4 <0=> Input <1=> Output <2=> I2SDO <3=> AC_SDATA_OUT
;// <o1.6..7> GPE3 <0=> Input <1=> Output <2=> I2SDI <3=> AC_SDATA_IN
;// <o1.4..5> GPE2 <0=> Input <1=> Output <2=> CDCLK <3=> AC_nRESET
;// <o1.2..3> GPE1 <0=> Input <1=> Output <2=> I2SSCLK <3=> AC_BIT_CLK
;// <o1.0..1> GPE0 <0=> Input <1=> Output <2=> I2SLRCK <3=> AC_SYNC
;// </h>
;// <h> Port E Pull-up Settings Register (GPEUP)
;// <o2.13> GPE13 Pull-up Disable
;// <o2.12> GPE12 Pull-up Disable
;// <o2.11> GPE11 Pull-up Disable
;// <o2.10> GPE10 Pull-up Disable
;// <o2.9> GPE9 Pull-up Disable
;// <o2.8> GPE8 Pull-up Disable
;// <o2.7> GPE7 Pull-up Disable
;// <o2.6> GPE6 Pull-up Disable
;// <o2.5> GPE5 Pull-up Disable
;// <o2.4> GPE4 Pull-up Disable
;// <o2.3> GPE3 Pull-up Disable
;// <o2.2> GPE2 Pull-up Disable
;// <o2.1> GPE1 Pull-up Disable
;// <o2.0> GPE0 Pull-up Disable
;// </h>
;// </e>
GPE_SETUP EQU 0
GPECON_Val EQU 0x00000000
GPEUP_Val EQU 0x00000000;// <e> Port F Settings
;// <h> Port F Control Register (GPFCON)
;// <o1.14..15> GPF7 <0=> Input <1=> Output <2=> EINT[7] <3=> Reserved
;// <o1.12..13> GPF6 <0=> Input <1=> Output <2=> EINT[6] <3=> Reserved
;// <o1.10..11> GPF5 <0=> Input <1=> Output <2=> EINT[5] <3=> Reserved
;// <o1.8..9> GPF4 <0=> Input <1=> Output <2=> EINT[4] <3=> Reserved
;// <o1.6..7> GPF3 <0=> Input <1=> Output <2=> EINT[3] <3=> Reserved
;// <o1.4..5> GPF2 <0=> Input <1=> Output <2=> EINT[2] <3=> Reserved
;// <o1.2..3> GPF1 <0=> Input <1=> Output <2=> EINT[1] <3=> Reserved
;// <o1.0..1> GPF0 <0=> Input <1=> Output <2=> EINT[0] <3=> Reserved
;// </h>
;// <h> Port F Pull-up Settings Register (GPFUP)
;// <o2.7> GPF7 Pull-up Disable
;// <o2.6> GPF6 Pull-up Disable
;// <o2.5> GPF5 Pull-up Disable
;// <o2.4> GPF4 Pull-up Disable
;// <o2.3> GPF3 Pull-up Disable
;// <o2.2> GPF2 Pull-up Disable
;// <o2.1> GPF1 Pull-up Disable
;// <o2.0> GPF0 Pull-up Disable
;// </h>
;// </e>
GPF_SETUP EQU 0
GPFCON_Val EQU 0x00000000
GPFUP_Val EQU 0x00000000;// <e> Port G Settings
;// <h> Port G Control Register (GPGCON)
;// <o1.30..31> GPG15 <0=> Input <1=> Output <2=> EINT[23] <3=> Reserved
;// <o1.28..29> GPG14 <0=> Input <1=> Output <2=> EINT[22] <3=> Reserved
;// <o1.26..27> GPG13 <0=> Input <1=> Output <2=> EINT[21] <3=> Reserved
;// <o1.24..25> GPG12 <0=> Input <1=> Output <2=> EINT[20] <3=> Reserved
;// <o1.22..23> GPG11 <0=> Input <1=> Output <2=> EINT[19] <3=> TCLK[1]
;// <o1.20..21> GPG10 <0=> Input <1=> Output <2=> EINT[18] <3=> nCTS1
;// <o1.18..19> GPG9 <0=> Input <1=> Output <2=> EINT[17] <3=> nRTS1
;// <o1.16..17> GPG8 <0=> Input <1=> Output <2=> EINT[16] <3=> Reserved
;// <o1.14..15> GPG7 <0=> Input <1=> Output <2=> EINT[15] <3=> SPICLK1
;// <o1.12..13> GPG6 <0=> Input <1=> Output <2=> EINT[14] <3=> SPIMOSI1
;// <o1.10..11> GPG5 <0=> Input <1=> Output <2=> EINT[13] <3=> SPIMISO1
;// <o1.8..9> GPG4 <0=> Input <1=> Output <2=> EINT[12] <3=> LCD_PWRDN
;// <o1.6..7> GPG3 <0=> Input <1=> Output <2=> EINT[11] <3=> nSS1
;// <o1.4..5> GPG2 <0=> Input <1=> Output <2=> EINT[10] <3=> nSS0
;// <o1.2..3> GPG1 <0=> Input <1=> Output <2=> EINT[9] <3=> Reserved
;// <o1.0..1> GPG0 <0=> Input <1=> Output <2=> EINT[8] <3=> Reserved
;// </h>
;// <h> Port G Pull-up Settings Register (GPGUP)
;// <o2.15> GPG15 Pull-up Disable
;// <o2.14> GPG14 Pull-up Disable
;// <o2.13> GPG13 Pull-up Disable
;// <o2.12> GPG12 Pull-up Disable
;// <o2.11> GPG11 Pull-up Disable
;// <o2.10> GPG10 Pull-up Disable
;// <o2.9> GPG9 Pull-up Disable
;// <o2.8> GPG8 Pull-up Disable
;// <o2.7> GPG7 Pull-up Disable
;// <o2.6> GPG6 Pull-up Disable
;// <o2.5> GPG5 Pull-up Disable
;// <o2.4> GPG4 Pull-up Disable
;// <o2.3> GPG3 Pull-up Disable
;// <o2.2> GPG2 Pull-up Disable
;// <o2.1> GPG1 Pull-up Disable
;// <o2.0> GPG0 Pull-up Disable
;// </h>
;// </e>
GPG_SETUP EQU 0
GPGCON_Val EQU 0x00000000
GPGUP_Val EQU 0x00000000;// <e> Port H Settings
;// <h> Port H Control Register (GPHCON)
;// <o1.20..21> GPH10 <0=> Input <1=> Output <2=> CLKOUT1 <3=> Reserved
;// <o1.18..19> GPH9 <0=> Input <1=> Output <2=> CLKOUT0 <3=> Reserved
;// <o1.16..17> GPH8 <0=> Input <1=> Output <2=> UEXTCLK <3=> Reserved
;// <o1.14..15> GPH7 <0=> Input <1=> Output <2=> RXD[2] <3=> nCTS1
;// <o1.12..13> GPH6 <0=> Input <1=> Output <2=> TXD[2] <3=> nRTS1
;// <o1.10..11> GPH5 <0=> Input <1=> Output <2=> RXD[1] <3=> Reserved
;// <o1.8..9> GPH4 <0=> Input <1=> Output <2=> TXD[1] <3=> Reserved
;// <o1.6..7> GPH3 <0=> Input <1=> Output <2=> RXD[0] <3=> Reserved
;// <o1.4..5> GPH2 <0=> Input <1=> Output <2=> TXD[0] <3=> Reserved
;// <o1.2..3> GPH1 <0=> Input <1=> Output <2=> nRTS0 <3=> Reserved
;// <o1.0..1> GPH0 <0=> Input <1=> Output <2=> nCTS0 <3=> Reserved
;// </h>
;// <h> Port H Pull-up Settings Register (GPHUP)
;// <o2.10> GPH10 Pull-up Disable
;// <o2.9> GPH9 Pull-up Disable
;// <o2.8> GPH8 Pull-up Disable
;// <o2.7> GPH7 Pull-up Disable
;// <o2.6> GPH6 Pull-up Disable
;// <o2.5> GPH5 Pull-up Disable
;// <o2.4> GPH4 Pull-up Disable
;// <o2.3> GPH3 Pull-up Disable
;// <o2.2> GPH2 Pull-up Disable
;// <o2.1> GPH1 Pull-up Disable
;// <o2.0> GPH0 Pull-up Disable
;// </h>
;// </e>
GPH_SETUP EQU 0
GPHCON_Val EQU 0x00000000
GPHUP_Val EQU 0x00000000 ;// <e> Port J Settings
;// <h> Port J Control Register (GPJCON)
;// <o1.24..25> GPJ12 <0=> Input <1=> Output <2=> CAMRESET <3=> Reserved
;// <o1.22..23> GPJ11 <0=> Input <1=> Output <2=> CAMCLKOUT <3=> Reserved
;// <o1.20..21> GPJ10 <0=> Input <1=> Output <2=> CAMHREF <3=> Reserved
;// <o1.18..19> GPJ9 <0=> Input <1=> Output <2=> CAMVSYNC <3=> Reserved
;// <o1.16..17> GPJ8 <0=> Input <1=> Output <2=> CAMPCLK <3=> Reserved
;// <o1.14..15> GPJ7 <0=> Input <1=> Output <2=> CAMDATA[7] <3=> Reserved
;// <o1.12..13> GPJ6 <0=> Input <1=> Output <2=> CAMDATA[6] <3=> Reserved
;// <o1.10..11> GPJ5 <0=> Input <1=> Output <2=> CAMDATA[5] <3=> Reserved
;// <o1.8..9> GPJ4 <0=> Input <1=> Output <2=> CAMDATA[4] <3=> Reserved
;// <o1.6..7> GPJ3 <0=> Input <1=> Output <2=> CAMDATA[3] <3=> Reserved
;// <o1.4..5> GPJ2 <0=> Input <1=> Output <2=> CAMDATA[2] <3=> Reserved
;// <o1.2..3> GPJ1 <0=> Input <1=> Output <2=> CAMDATA[1] <3=> Reserved
;// <o1.0..1> GPJ0 <0=> Input <1=> Output <2=> CAMDATA[0] <3=> Reserved
;// </h>
;// <h> Port J Pull-up Settings Register (GPJUP)
;// <o2.12> GPJ12 Pull-up Disable
;// <o2.11> GPJ11 Pull-up Disable
;// <o2.10> GPJ10 Pull-up Disable
;// <o2.9> GPJ9 Pull-up Disable
;// <o2.8> GPJ8 Pull-up Disable
;// <o2.7> GPJ7 Pull-up Disable
;// <o2.6> GPJ6 Pull-up Disable
;// <o2.5> GPJ5 Pull-up Disable
;// <o2.4> GPJ4 Pull-up Disable
;// <o2.3> GPJ3 Pull-up Disable
;// <o2.2> GPJ2 Pull-up Disable
;// <o2.1> GPJ1 Pull-up Disable
;// <o2.0> GPJ0 Pull-up Disable
;// </h>
;// </e>
GPJ_SETUP EQU 0
GPJCON_Val EQU 0x00000000
GPJUP_Val EQU 0x00000000;// </e> I/O SetupMACRO
$HandlerLabel HANDLER $HandleLabel$HandlerLabelsub sp,sp,#4 ;decrement sp(to store jump address)stmfd sp!,{r0} ;PUSH the work register to stack(lr does not push because it return to original address)ldr r0,=$HandleLabel;load the address of HandleXXX to r0ldr r0,[r0] ;load the contents(service routine start address) of HandleXXXstr r0,[sp,#4] ;store the contents(ISR) of HandleXXX to stackldmfd sp!,{r0,pc} ;POP the work register and pc(jump to ISR)MEND;----------------------- CODE --------------------------------------------------PRESERVE8; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to run.AREA RESET, CODE, READONLYARMIF :LNOT::DEF:__EVAL IMPORT ||Image$$ER_ROM1$$RO$$Length||IMPORT ||Image$$RW_RAM1$$RW$$Length||ENDIF; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.EXPORT __ENTRY
__ENTRYVectors LDR PC, Reset_Addr LDR PC, Undef_AddrLDR PC, SWI_AddrLDR PC, PAbt_AddrLDR PC, DAbt_AddrIF :DEF:__EVALDCD 0x4000ELSE DCD ||Image$$ER_ROM1$$RO$$Length||+\||Image$$RW_RAM1$$RW$$Length||ENDIFLDR PC, IRQ_AddrLDR PC, FIQ_AddrIF :DEF:__RTXIMPORT SWI_HandlerIMPORT IRQ_Handler_RTXENDIFReset_Addr DCD Reset_Handler
Undef_Addr DCD Undef_Handler
SWI_Addr DCD SWI_Handler
PAbt_Addr DCD PAbt_Handler
DAbt_Addr DCD DAbt_HandlerDCD 0 ; Reserved Address IF :DEF:__RTX
IRQ_Addr DCD IRQ_Handler_RTXELSE
IRQ_Addr DCD IRQ_HandlerENDIF
FIQ_Addr DCD FIQ_Handler;Undef_Handler B Undef_Handler;IF :DEF:__RTX;ELSE
;SWI_Handler B SWI_Handler;ENDIF
;PAbt_Handler B PAbt_Handler
;DAbt_Handler B DAbt_Handler
;IRQ_Handler PROC;EXPORT IRQ_Handler [WEAK];B .;ENDP
;FIQ_Handler B FIQ_HandlerFIQ_Handler HANDLER HandleFIQ
HandlerIRQ HANDLER HandleIRQ
Undef_Handler HANDLER HandleUndef
SWI_Handler HANDLER HandleSWI
DAbt_Handler HANDLER HandleDabort
PAbt_Handler HANDLER HandlePabort;呵呵,来了来了.好戏来了,这一段程序就是用来进行第二次查表的过程了.
;如果说第一次查表是由硬件来完成的,那这一次查表就是由软件来实现的了.
;为什么要查两次表??
;没有办法,ARM把所有的中断都归纳成一个IRQ中断异常和一个FIRQ中断异常
;第一次查表主要是查出是什么异常,可我们总要知道是这个中断异常中的什么中断呀!
;没办法了,再查一次表呗!
;===================================================================================
;外部中断号判断，通过中断服务程序入口地址存储器的地址偏移确定
;PC=[HandleEINT0+[INTOFFSET]]
;IsrIRQ
IRQ_Handlersub sp,sp,#4 ;给PC寄存器保留 reserved for PCstmfd sp!,{r8-r9} ;把r8-r9压入栈ldr r9,=INTOFFSET ;把INTOFFSET的地址装入r9 INTOFFSET是一个内部的寄存器,存着中断的偏移ldr r9,[r9] ;I_ISRldr r8,=HandleEINT0 ;这就是我们第二个中断向量表的入口的,先装入r8
;===================================================================================
;哈哈,这查表方法够好了吧,r8(入口)+index*4(别望了一条指令是4 bytes的喔),
;这不就是我们要找的那一项了吗.找到了表项,下一步做什么?肯定先装入了!
;==================================================================================add r8,r8,r9,lsl #2 ;地址对齐，因为每个中断向量占4个字节，即isr = IvectTable + Offeset * 4ldr r8,[r8] ;装入中断服务程序的入口str r8,[sp,#8] ;把入口也入栈,准备用旧招ldmfd sp!,{r8-r9,pc} ;施招,弹出栈,哈哈,顺便把r8弹出到PC了,跳转成功!; Reset HandlerEXPORT Reset_Handler
Reset_Handler ; Watchdog Setup ---------------------------------------------------------------IF WT_SETUP != 0LDR R0, =WT_BASELDR R1, =WTCON_ValLDR R2, =WTDAT_ValSTR R2, [R0, #WTCNT_OFS]STR R2, [R0, #WTDAT_OFS]STR R1, [R0, #WTCON_OFS]ENDIF; Clock Setup ------------------------------------------------------------------IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0)LDR R0, =CLOCK_BASELDR R1, =LOCKTIME_ValSTR R1, [R0, #LOCKTIME_OFS]MOV R1, #CLKDIVN_Val STR R1, [R0, #CLKDIVN_OFS]LDR R1, =CAMDIVN_ValSTR R1, [R0, #CAMDIVN_OFS]LDR R1, =MPLLCON_ValSTR R1, [R0, #MPLLCON_OFS]LDR R1, =UPLLCON_ValSTR R1, [R0, #UPLLCON_OFS]MOV R1, #CLKSLOW_ValSTR R1, [R0, #CLKSLOW_OFS]LDR R1, =CLKCON_ValSTR R1, [R0, #CLKCON_OFS]ENDIF; Memory Controller Setup ------------------------------------------------------IF (:LNOT:(:DEF:NO_MC_SETUP)):LAND:(CLOCK_SETUP != 0)LDR R0, =MC_BASELDR R1, =BWSCON_ValSTR R1, [R0, #BWSCON_OFS]LDR R1, =BANKCON0_ValSTR R1, [R0, #BANKCON0_OFS]LDR R1, =BANKCON1_ValSTR R1, [R0, #BANKCON1_OFS]LDR R1, =BANKCON2_ValSTR R1, [R0, #BANKCON2_OFS]LDR R1, =BANKCON3_ValSTR R1, [R0, #BANKCON3_OFS]LDR R1, =BANKCON4_ValSTR R1, [R0, #BANKCON4_OFS]LDR R1, =BANKCON5_ValSTR R1, [R0, #BANKCON5_OFS]LDR R1, =BANKCON6_ValSTR R1, [R0, #BANKCON6_OFS]LDR R1, =BANKCON7_ValSTR R1, [R0, #BANKCON7_OFS]LDR R1, =REFRESH_ValSTR R1, [R0, #REFRESH_OFS]MOV R1, #BANKSIZE_ValSTR R1, [R0, #BANKSIZE_OFS]MOV R1, #MRSRB6_ValSTR R1, [R0, #MRSRB6_OFS]MOV R1, #MRSRB7_ValSTR R1, [R0, #MRSRB7_OFS]ENDIF ; I/O Pins Setup ---------------------------------------------------------------IF (:LNOT:(:DEF:NO_GP_SETUP)):LAND:(GP_SETUP != 0)IF GPA_SETUP != 0LDR R0, =GPA_BASELDR R1, =GPACON_ValSTR R1, [R0, #GPCON_OFS]ENDIFIF GPB_SETUP != 0LDR R0, =GPB_BASELDR R1, =GPBCON_ValSTR R1, [R0, #GPCON_OFS]LDR R1, =GPBUP_ValSTR R1, [R0, #GPUP_OFS]ENDIFIF GPC_SETUP != 0LDR R0, =GPC_BASELDR R1, =GPCCON_ValSTR R1, [R0, #GPCON_OFS]LDR R1, =GPCUP_ValSTR R1, [R0, #GPUP_OFS]ENDIFIF GPD_SETUP != 0LDR R0, =GPD_BASELDR R1, =GPDCON_ValSTR R1, [R0, #GPCON_OFS]LDR R1, =GPDUP_ValSTR R1, [R0, #GPUP_OFS]ENDIFIF GPE_SETUP != 0LDR R0, =GPE_BASELDR R1, =GPECON_ValSTR R1, [R0, #GPCON_OFS]LDR R1, =GPEUP_ValSTR R1, [R0, #GPUP_OFS]ENDIFIF GPF_SETUP != 0LDR R0, =GPF_BASELDR R1, =GPFCON_ValSTR R1, [R0, #GPCON_OFS]LDR R1, =GPFUP_ValSTR R1, [R0, #GPUP_OFS]ENDIFIF GPG_SETUP != 0LDR R0, =GPG_BASELDR R1, =GPGCON_ValSTR R1, [R0, #GPCON_OFS]LDR R1, =GPGUP_ValSTR R1, [R0, #GPUP_OFS]ENDIFIF GPH_SETUP != 0LDR R0, =GPH_BASELDR R1, =GPHCON_ValSTR R1, [R0, #GPCON_OFS]LDR R1, =GPHUP_ValSTR R1, [R0, #GPUP_OFS]ENDIFIF GPJ_SETUP != 0LDR R0, =GPJ_BASELDR R1, =GPJCON_ValSTR R1, [R0, #GPCON_OFS]LDR R1, =GPJUP_ValSTR R1, [R0, #GPUP_OFS]ENDIFENDIF; Copy Exception Vectors to Internal RAM ---------------------------------------IF :DEF:RAM_INTVECADR R8, Vectors ; SourceLDR R9, =IRAM_BASE ; DestinationLDMIA R8!, {R0-R7} ; Load Vectors STMIA R9!, {R0-R7} ; Store Vectors LDMIA R8!, {R0-R7} ; Load Handler Addresses STMIA R9!, {R0-R7} ; Store Handler AddressesENDIF; Setup Stack for each mode ----------------------------------------------------LDR R0, =Stack_Top; Enter Undefined Instruction Mode and set its Stack PointerMSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_BitMOV SP, R0SUB R0, R0, #UND_Stack_Size; Enter Abort Mode and set its Stack PointerMSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_BitMOV SP, R0SUB R0, R0, #ABT_Stack_Size; Enter FIQ Mode and set its Stack PointerMSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_BitMOV SP, R0SUB R0, R0, #FIQ_Stack_Size; Enter IRQ Mode and set its Stack PointerMSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_BitMOV SP, R0SUB R0, R0, #IRQ_Stack_Size; Enter Supervisor Mode and set its Stack Pointer;MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_BitMSR CPSR_c, #Mode_SVC:OR:F_BitMOV SP, R0SUB R0, R0, #SVC_Stack_Size; Enter User Mode and set its Stack Pointer;MSR CPSR_c, #Mode_USR;MSR CPSR_c, #Mode_USR:OR:I_Bit:OR:F_Bit;MOV SP, R0;SUB SL, SP, #USR_Stack_Size; Enter User Mode and set its Stack Pointer;MSR CPSR_c, #Mode_USRIF :DEF:__MICROLIBEXPORT __initial_spELSEMOV SP, R0SUB SL, SP, #USR_Stack_SizeENDIF; Enter the C code -------------------------------------------------------------IMPORT __mainLDR R0, =__mainBX R0IF :DEF:__MICROLIBEXPORT __heap_baseEXPORT __heap_limitELSE
; User Initial Stack & HeapAREA |.text|, CODE, READONLYIMPORT __use_two_region_memoryEXPORT __user_initial_stackheap
__user_initial_stackheapLDR R0, = Heap_MemLDR R1, =(Stack_Mem + USR_Stack_Size)LDR R2, = (Heap_Mem + Heap_Size)LDR R3, = Stack_MemBX LRENDIFALIGNAREA RamData, DATA, READWRITE^ _ISR_STARTADDRESS ; _ISR_STARTADDRESS=0x33FF_FF00
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4;Do not use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
;@0x33FF_FF20
HandleEINT0 # 4
HandleEINT1 # 4
HandleEINT2 # 4
HandleEINT3 # 4
HandleEINT4_7 # 4
HandleEINT8_23 # 4
HandleCAM # 4 ; Added for 2440.
HandleBATFLT # 4
HandleTICK # 4
HandleWDT # 4
HandleTIMER0 # 4
HandleTIMER1 # 4
HandleTIMER2 # 4
HandleTIMER3 # 4
HandleTIMER4 # 4
HandleUART2 # 4
;@0x33FF_FF60
HandleLCD # 4
HandleDMA0 # 4
HandleDMA1 # 4
HandleDMA2 # 4
HandleDMA3 # 4
HandleMMC # 4
HandleSPI0 # 4
HandleUART1 # 4
HandleNFCON # 4 ; Added for 2440.
HandleUSBD # 4
HandleUSBH # 4
HandleIIC # 4
HandleUART0 # 4
HandleSPI1 # 4
HandleRTC # 4
HandleADC # 4
;@0x33FF_FFA0END
二、代码
main.c
#include "S3C2440.h"
#include "led.h"
#include "uart.h"void __use_two_region_memory(void)
{}int __main()
{UART0_Init();LED_Init();LED1_ON();while(1){}}
uart.c
#include "S3C2440.h"
#include "led.h"void UART0_putc(unsigned char c);
unsigned char UART0_getc(void);//中断服务函数
void __irq UART0_handler(void)
{unsigned char c;SUBSRCPND |= 0x3;SRCPND |= 0x1<<28;INTPND |= 0x1<<28;c=UART0_getc();delay(1000);UART0_putc(c);
}void UART0_Init(void)
{//设置GPH端口UART0模式,使能内部上拉GPHCON &= ~((3<<4)|(3<<6));GPHCON |= (2<<4)|(2<<6); //GPH2-TXD, GPH3-RXDGPHUP &= ~((1<<2)|(1<<3)); //GPH2,GPH3 使能上拉//UART0配置ULCON0=0X03;/*8位数据位,无校验，1个停止位*/UCON0=0X005;/*PCLK时钟源50MHz，正常模式，中断/查询模式*/UFCON0=0X00;/*7:0设置FIFO寄存器，默认0*/UMCON0=0X00;/*7:0设置modem寄存器，默认0*//* 设置波特率BRDIVn = (int)( UART clock / ( buad rate x 16) ) –1UART clock =PCLK= 50MUBRDIVn = (int)( 50000000 / ( 115200 x 16) ) –1 = 26*/UBRDIV0=26;//UART0中断配置SRCPND |= 0x1<<28;/*清除UART0中断*/SUBSRCPND |= 0x3;/*清除UART0收发中断*/INTPND |= 0x1<<28;/*清除UART0中断*/INTSUBMSK &= ~(0x1);/*打开UART0接收中断，使能中断*/INTSUBMSK |= (0x1<<1);/*关闭UART0发送中断，禁止中断*/INTMSK &= ~(0x1<<28);/*打开UART0中断，使能中断*/pISR_UART0=(unsigned)UART0_handler;/*连接中断服务函数*/
}void UART0_putc(unsigned char c)
{while(!(UTRSTAT0&(1<<2)));UTXH0=c;}unsigned char UART0_getc(void)
{while(!(UTRSTAT0 & (1<<0)));return URXH0;
}
uart.h
#ifndef __UART_H
#define __UART_Hvoid UART0_Init(void);
void UART0_putc(unsigned char c);
unsigned char UART0_getc(void);#endif
led.c
#include "S3C2440.h"//开发板4个LED初始化
void LED_Init(void)
{GPBCON = ((GPBCON|0X15400)&0X3D57FF);GPBDAT = GPBDAT|0X1E0;
}//打开开发板的LED1
void LED1_ON(void)
{GPBDAT = GPBDAT&0X7DF;
}//打开开发板的LED4
void LED4_ON(void)
{GPBDAT = GPBDAT&0X6FF;
}//关闭开发板的LED4
void LED4_OFF(void)
{GPBDAT = GPBDAT|0X100;
}void delay(int temp)
{while(temp)temp--;
}
led.h
#ifndef __LED_H
#define __LED_Hvoid LED_Init(void);
void LED1_ON(void);
void LED4_ON(void);
void LED4_OFF(void);void delay(unsigned temp);#endif
S3C2440.h
/***********************************************************************/
/* This file is part of the uVision/ARM development tools */
/* Copyright KEIL - An ARM Company 2002-2007 */
/***********************************************************************/
/* */
/* S3C2440.H: Header file for Samsung S3C2440 */
/* */
/***********************************************************************/#ifndef __S3C2440_H
#define __S3C2440_H#define _ISR_STARTADDRESS 0x33ffff00// Memory Controllers
#define BWSCON (*(volatile unsigned long *) 0x48000000)
#define BANKCON0 (*(volatile unsigned long *) 0x48000004)
#define BANKCON1 (*(volatile unsigned long *) 0x48000008)
#define BANKCON2 (*(volatile unsigned long *) 0x4800000C)
#define BANKCON3 (*(volatile unsigned long *) 0x48000010)
#define BANKCON4 (*(volatile unsigned long *) 0x48000014)
#define BANKCON5 (*(volatile unsigned long *) 0x48000018)
#define BANKCON6 (*(volatile unsigned long *) 0x4800001C)
#define BANKCON7 (*(volatile unsigned long *) 0x48000020)
#define REFRESH (*(volatile unsigned long *) 0x48000024)
#define BANKSIZE (*(volatile unsigned long *) 0x48000028)
#define MRSRB6 (*(volatile unsigned long *) 0x4800002C)
#define MRSRB7 (*(volatile unsigned long *) 0x48000030)// USB Host Controller
#define HcRevision (*(volatile unsigned long *) 0x49000000)
#define HcControl (*(volatile unsigned long *) 0x49000004)
#define HcCommonStatus (*(volatile unsigned long *) 0x49000008)
#define HcInterruptStatus (*(volatile unsigned long *) 0x4900000C)
#define HcInterruptEnable (*(volatile unsigned long *) 0x49000010)
#define HcInterruptDisable (*(volatile unsigned long *) 0x49000014)
#define HcHCCA (*(volatile unsigned long *) 0x49000018)
#define HcPeriodCuttentED (*(volatile unsigned long *) 0x4900001C)
#define HcControlHeadED (*(volatile unsigned long *) 0x49000020)
#define HcControlCurrentED (*(volatile unsigned long *) 0x49000024)
#define HcBulkHeadED (*(volatile unsigned long *) 0x49000028)
#define HcBulkCurrentED (*(volatile unsigned long *) 0x4900002C)
#define HcDoneHead (*(volatile unsigned long *) 0x49000030)
#define HcRmInterval (*(volatile unsigned long *) 0x49000034)
#define HcFmRemaining (*(volatile unsigned long *) 0x49000038)
#define HcFmNumber (*(volatile unsigned long *) 0x4900003C)
#define HcPeriodicStart (*(volatile unsigned long *) 0x49000040)
#define HcLSTreshold (*(volatile unsigned long *) 0x49000044)
#define HcRhDescriptorA (*(volatile unsigned long *) 0x49000048)
#define HcRhDescriptorB (*(volatile unsigned long *) 0x4900004C)
#define HcRhStatus (*(volatile unsigned long *) 0x49000050)
#define HcRhPortStatus1 (*(volatile unsigned long *) 0x49000054)
#define HcRhPortStatus2 (*(volatile unsigned long *) 0x49000058)// Interrupt Controller
#define SRCPND (*(volatile unsigned long *) 0x4A000000)
#define INTMOD (*(volatile unsigned long *) 0x4A000004)
#define INTMSK (*(volatile unsigned long *) 0x4A000008)
#define PRIORITY (*(volatile unsigned long *) 0x4A00000C)
#define INTPND (*(volatile unsigned long *) 0x4A000010)
#define INTOFFSET (*(volatile unsigned long *) 0x4A000014)
#define SUBSRCPND (*(volatile unsigned long *) 0x4A000018)
#define INTSUBMSK (*(volatile unsigned long *) 0x4A00001C)// DMA
#define DISRC0 (*(volatile unsigned long *) 0x4B000000)
#define DISRCC0 (*(volatile unsigned long *) 0x4B000004)
#define DIDST0 (*(volatile unsigned long *) 0x4B000008)
#define DIDSTC0 (*(volatile unsigned long *) 0x4B00000C)
#define DCON0 (*(volatile unsigned long *) 0x4B000010)
#define DSTAT0 (*(volatile unsigned long *) 0x4B000014)
#define DCSRC0 (*(volatile unsigned long *) 0x4B000018)
#define DCDST0 (*(volatile unsigned long *) 0x4B00001C)
#define DMASKTRIG0 (*(volatile unsigned long *) 0x4B000020)#define DISRC1 (*(volatile unsigned long *) 0x4B000040)
#define DISRCC1 (*(volatile unsigned long *) 0x4B000044)
#define DIDST1 (*(volatile unsigned long *) 0x4B000048)
#define DIDSTC1 (*(volatile unsigned long *) 0x4B00004C)
#define DCON1 (*(volatile unsigned long *) 0x4B000050)
#define DSTAT1 (*(volatile unsigned long *) 0x4B000054)
#define DCSRC1 (*(volatile unsigned long *) 0x4B000058)
#define DCDST1 (*(volatile unsigned long *) 0x4B00005C)
#define DMASKTRIG1 (*(volatile unsigned long *) 0x4B000060)#define DISRC2 (*(volatile unsigned long *) 0x4B000080)
#define DISRCC2 (*(volatile unsigned long *) 0x4B000084)
#define DIDST2 (*(volatile unsigned long *) 0x4B000088)
#define DIDSTC2 (*(volatile unsigned long *) 0x4B00008C)
#define DCON2 (*(volatile unsigned long *) 0x4B000090)
#define DSTAT2 (*(volatile unsigned long *) 0x4B000094)
#define DCSRC2 (*(volatile unsigned long *) 0x4B000098)
#define DCDST2 (*(volatile unsigned long *) 0x4B00009C)
#define DMASKTRIG2 (*(volatile unsigned long *) 0x4B0000a0)#define DISRC3 (*(volatile unsigned long *) 0x4B0000C0)
#define DISRCC3 (*(volatile unsigned long *) 0x4B0000C4)
#define DIDST3 (*(volatile unsigned long *) 0x4B0000C8)
#define DIDSTC3 (*(volatile unsigned long *) 0x4B0000CC)
#define DCON3 (*(volatile unsigned long *) 0x4B0000D0)
#define DSTAT3 (*(volatile unsigned long *) 0x4B0000D4)
#define DCSRC3 (*(volatile unsigned long *) 0x4B0000D8)
#define DCDST3 (*(volatile unsigned long *) 0x4B0000DC)
#define DMASKTRIG3 (*(volatile unsigned long *) 0x4B0000E0)// Clock & Power Management
#define LOCKTIME (*(volatile unsigned long *) 0x4C000000)
#define MPLLCON (*(volatile unsigned long *) 0x4C000004)
#define UPLLCON (*(volatile unsigned long *) 0x4C000008)
#define CLKCON (*(volatile unsigned long *) 0x4C00000C)
#define CLKSLOW (*(volatile unsigned long *) 0x4C000010)
#define CLKDIVN (*(volatile unsigned long *) 0x4C000014)
#define CAMDIVN (*(volatile unsigned long *) 0x4C000018)// LCD Controller
#define LCDCON1 (*(volatile unsigned long *) 0x4D000000)
#define LCDCON2 (*(volatile unsigned long *) 0x4D000004)
#define LCDCON3 (*(volatile unsigned long *) 0x4D000008)
#define LCDCON4 (*(volatile unsigned long *) 0x4D00000C)
#define LCDCON5 (*(volatile unsigned long *) 0x4D000010)
#define LCDSADDR1 (*(volatile unsigned long *) 0x4D000014)
#define LCDSADDR2 (*(volatile unsigned long *) 0x4D000018)
#define LCDSADDR3 (*(volatile unsigned long *) 0x4D00001C)
#define REDLUT (*(volatile unsigned long *) 0x4D000020)
#define GREENLUT (*(volatile unsigned long *) 0x4D000024)
#define BLUELUT (*(volatile unsigned long *) 0x4D000028)
#define DITHMODE (*(volatile unsigned long *) 0x4D00004C)
#define TPAL (*(volatile unsigned long *) 0x4D000050)
#define LCDINTPND (*(volatile unsigned long *) 0x4D000054)
#define LCDSRCPND (*(volatile unsigned long *) 0x4D000058)
#define LCDINTMSK (*(volatile unsigned long *) 0x4D00005C)
#define LPCSEL (*(volatile unsigned long *) 0x4D000060)
#define PALETTE 0x4D000400// NAND flash
#define NFCONF (*(volatile unsigned long *) 0x4E000000)
#define NFCONT (*(volatile unsigned long *) 0x4E000004)
#define NFCMD (*(volatile unsigned long *) 0x4E000008)
#define NFADDR (*(volatile unsigned long *) 0x4E00000C)
#define NFDATA (*(volatile unsigned long *) 0x4E000010)
#define NFMECCD0 (*(volatile unsigned long *) 0x4E000014)
#define NFMECCD1 (*(volatile unsigned long *) 0x4E000018)
#define NFSECCD (*(volatile unsigned long *) 0x4E00001C)
#define NFSTAT (*(volatile unsigned long *) 0x4E000020)
#define NFESTAT0 (*(volatile unsigned long *) 0x4E000024)
#define NFESTAT1 (*(volatile unsigned long *) 0x4E000028)
#define NFMECC0 (*(volatile unsigned long *) 0x4E00002C)
#define NFMECC1 (*(volatile unsigned long *) 0x4E000030)
#define NFSECC (*(volatile unsigned long *) 0x4E000034)
#define NFSBLK (*(volatile unsigned long *) 0x4E000038)
#define NFEBLK (*(volatile unsigned long *) 0x4E00003C)// Camera Interface
#define CISRCFMT (*(volatile unsigned long *) 0x4F000000)
#define CIWDOFST (*(volatile unsigned long *) 0x4F000004)
#define CIGCTRL (*(volatile unsigned long *) 0x4F000008)
#define CICOYSA1 (*(volatile unsigned long *) 0x4F000018)
#define CICOYSA2 (*(volatile unsigned long *) 0x4F00001C)
#define CICOYSA3 (*(volatile unsigned long *) 0x4F000020)
#define CICOYSA4 (*(volatile unsigned long *) 0x4F000024)
#define CICOCBSA1 (*(volatile unsigned long *) 0x4F000028)
#define CICOCBSA2 (*(volatile unsigned long *) 0x4F00002C)
#define CICOCBSA3 (*(volatile unsigned long *) 0x4F000030)
#define CICOCBSA4 (*(volatile unsigned long *) 0x4F000034)
#define CICORSA1 (*(volatile unsigned long *) 0x4F000038)
#define CICORSA2 (*(volatile unsigned long *) 0x4F00003C)
#define CICORSA3 (*(volatile unsigned long *) 0x4F000040)
#define CICORSA4 (*(volatile unsigned long *) 0x4F000044)
#define CICOTRGFMT (*(volatile unsigned long *) 0x4F000048)
#define CICOCTRL (*(volatile unsigned long *) 0x4F00004C)
#define CICOSCPRERATIO (*(volatile unsigned long *) 0x4F000050)
#define CICOSCPREDST (*(volatile unsigned long *) 0x4F000054)
#define CICOSCCTRL (*(volatile unsigned long *) 0x4F000058)
#define CICOTAREA (*(volatile unsigned long *) 0x4F00005C)
#define CICOSTATUS (*(volatile unsigned long *) 0x4F000064)
#define CIPRCLRSA1 (*(volatile unsigned long *) 0x4F00006C)
#define CIPRCLRSA2 (*(volatile unsigned long *) 0x4F000070)
#define CIPRCLRSA3 (*(volatile unsigned long *) 0x4F000074)
#define CIPRCLRSA4 (*(volatile unsigned long *) 0x4F000078)
#define CIPRTRGFMT (*(volatile unsigned long *) 0x4F00007C)
#define CIPRCTRL (*(volatile unsigned long *) 0x4F000080)
#define CIPRSCPRERATIO (*(volatile unsigned long *) 0x4F000084)
#define CIPRSCPREDST (*(volatile unsigned long *) 0x4F000088)
#define CIPRSCCTRL (*(volatile unsigned long *) 0x4F00008C)
#define CIPRTAREA (*(volatile unsigned long *) 0x4F000090)
#define CIPRSTATUS (*(volatile unsigned long *) 0x4F000098)
#define CIIMGCPT (*(volatile unsigned long *) 0x4F0000A0)// UART
#define ULCON0 (*(volatile unsigned long *) 0x50000000)
#define UCON0 (*(volatile unsigned long *) 0x50000004)
#define UFCON0 (*(volatile unsigned long *) 0x50000008)
#define UMCON0 (*(volatile unsigned long *) 0x5000000C)
#define UTRSTAT0 (*(volatile unsigned long *) 0x50000010)
#define UERSTAT0 (*(volatile unsigned long *) 0x50000014)
#define UFSTAT0 (*(volatile unsigned long *) 0x50000018)
#define UMSTAT0 (*(volatile unsigned long *) 0x5000001C)
#define UTXH0 (*(volatile unsigned char *) 0x50000020)
#define URXH0 (*(volatile unsigned char *) 0x50000024)
#define UBRDIV0 (*(volatile unsigned long *) 0x50000028)#define ULCON1 (*(volatile unsigned long *) 0x50004000)
#define UCON1 (*(volatile unsigned long *) 0x50004004)
#define UFCON1 (*(volatile unsigned long *) 0x50004008)
#define UMCON1 (*(volatile unsigned long *) 0x5000400C)
#define UTRSTAT1 (*(volatile unsigned long *) 0x50004010)
#define UERSTAT1 (*(volatile unsigned long *) 0x50004014)
#define UFSTAT1 (*(volatile unsigned long *) 0x50004018)
#define UMSTAT1 (*(volatile unsigned long *) 0x5000401C)
#define UTXH1 (*(volatile unsigned char *) 0x50004020)
#define URXH1 (*(volatile unsigned char *) 0x50004024)
#define UBRDIV1 (*(volatile unsigned long *) 0x50004028)#define ULCON2 (*(volatile unsigned long *) 0x50008000)
#define UCON2 (*(volatile unsigned long *) 0x50008004)
#define UFCON2 (*(volatile unsigned long *) 0x50008008)
#define UMCON2 (*(volatile unsigned long *) 0x5000800C)
#define UTRSTAT2 (*(volatile unsigned long *) 0x50008010)
#define UERSTAT2 (*(volatile unsigned long *) 0x50008014)
#define UFSTAT2 (*(volatile unsigned long *) 0x50008018)
#define UTXH2 (*(volatile unsigned char *) 0x50008020)
#define URXH2 (*(volatile unsigned char *) 0x50008024)
#define UBRDIV2 (*(volatile unsigned long *) 0x50008028)#ifdef __BIG_ENDIAN
#undef UTXH0
#define UTXH0 (*(volatile unsigned char *) 0x50000023)
#undef URXH0
#define URXH0 (*(volatile unsigned char *) 0x50000027)
#undef UTXH1
#define UTXH1 (*(volatile unsigned char *) 0x50004023)
#undef URXH1
#define URXH1 (*(volatile unsigned char *) 0x50004027)
#undef UTXH2
#define UTXH2 (*(volatile unsigned char *) 0x50008023)
#undef URXH2
#define URXH2 (*(volatile unsigned char *) 0x50008027)
#endif// PWM Timer
#define TCFG0 (*(volatile unsigned long *) 0x51000000)
#define TCFG1 (*(volatile unsigned long *) 0x51000004)
#define TCON (*(volatile unsigned long *) 0x51000008)
#define TCNTB0 (*(volatile unsigned long *) 0x5100000C)
#define TCMPB0 (*(volatile unsigned long *) 0x51000010)
#define TCNTO0 (*(volatile unsigned long *) 0x51000014)
#define TCNTB1 (*(volatile unsigned long *) 0x51000018)
#define TCMPB1 (*(volatile unsigned long *) 0x5100001C)
#define TCNTO1 (*(volatile unsigned long *) 0x51000020)
#define TCNTB2 (*(volatile unsigned long *) 0x51000024)
#define TCMPB2 (*(volatile unsigned long *) 0x51000028)
#define TCNTO2 (*(volatile unsigned long *) 0x5100002C)
#define TCNTB3 (*(volatile unsigned long *) 0x51000030)
#define TCMPB3 (*(volatile unsigned long *) 0x51000034)
#define TCNTO3 (*(volatile unsigned long *) 0x51000038)
#define TCNTB4 (*(volatile unsigned long *) 0x5100003C)
#define TCNTO4 (*(volatile unsigned long *) 0x51000040)// USB Device
#ifdef __BIG_ENDIAN
#define FUNC_ADDR_REG (*(volatile unsigned char *) 0x52000143)
#define PWR_REG (*(volatile unsigned char *) 0x52000147)
#define EP_INT_REG (*(volatile unsigned char *) 0x5200014B)
#define USB_INT_REG (*(volatile unsigned char *) 0x5200015B)
#define EP_INT_EN_REG (*(volatile unsigned char *) 0x5200015F)
#define USB_INT_EN_REG (*(volatile unsigned char *) 0x5200016F)
#define FRAME_NUM1_REG (*(volatile unsigned char *) 0x52000173)
#define FRAME_NUM2_REG (*(volatile unsigned char *) 0x52000177)
#define INDEX_REG (*(volatile unsigned char *) 0x5200017B)
#define MAXP_REG (*(volatile unsigned char *) 0x52000183)
#define EP0_CSR (*(volatile unsigned char *) 0x52000187)
#define IN_CSR1_REG (*(volatile unsigned char *) 0x52000187)
#define IN_CSR2_REG (*(volatile unsigned char *) 0x5200018B)
#define OUT_CSR1_REG (*(volatile unsigned char *) 0x52000193)
#define OUT_CSR2_REG (*(volatile unsigned char *) 0x52000197)
#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *) 0x5200019B)
#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *) 0x5200019F)
#define EP0_FIFO (*(volatile unsigned char *) 0x520001C3)
#define EP1_FIFO (*(volatile unsigned char *) 0x520001C7)
#define EP2_FIFO (*(volatile unsigned char *) 0x520001CF)
#define EP3_FIFO (*(volatile unsigned char *) 0x520001CF)
#define EP4_FIFO (*(volatile unsigned char *) 0x520001D3)
#define EP1_DMA_CON (*(volatile unsigned char *) 0x52000203)
#define EP1_DMA_UNIT (*(volatile unsigned char *) 0x52000207)
#define EP1_DMA_FIFO (*(volatile unsigned char *) 0x5200020B)
#define EP1_DMA_TTC_L (*(volatile unsigned char *) 0x5200020F)
#define EP1_DMA_TTC_M (*(volatile unsigned char *) 0x52000213)
#define EP1_DMA_TTC_H (*(volatile unsigned char *) 0x52000217)
#define EP2_DMA_CON (*(volatile unsigned char *) 0x5200021B)
#define EP2_DMA_UNIT (*(volatile unsigned char *) 0x5200021F)
#define EP2_DMA_FIFO (*(volatile unsigned char *) 0x52000223)
#define EP2_DMA_TTC_L (*(volatile unsigned char *) 0x52000227)
#define EP2_DMA_TTC_M (*(volatile unsigned char *) 0x5200022B)
#define EP2_DMA_TTC_H (*(volatile unsigned char *) 0x5200022F)
#define EP3_DMA_CON (*(volatile unsigned char *) 0x52000243)
#define EP3_DMA_UNIT (*(volatile unsigned char *) 0x52000247)
#define EP3_DMA_FIFO (*(volatile unsigned char *) 0x5200024B)
#define EP3_DMA_TTC_L (*(volatile unsigned char *) 0x5200024F)
#define EP3_DMA_TTC_M (*(volatile unsigned char *) 0x52000253)
#define EP3_DMA_TTC_H (*(volatile unsigned char *) 0x52000257)
#define EP4_DMA_CON (*(volatile unsigned char *) 0x5200025B)
#define EP4_DMA_UNIT (*(volatile unsigned char *) 0x5200025F)
#define EP4_DMA_FIFO (*(volatile unsigned char *) 0x52000263)
#define EP4_DMA_TTC_L (*(volatile unsigned char *) 0x52000267)
#define EP4_DMA_TTC_M (*(volatile unsigned char *) 0x5200026B)
#define EP4_DMA_TTC_H (*(volatile unsigned char *) 0x5200026F)#else // Little Endian
#define FUNC_ADDR_REG (*(volatile unsigned char *) 0x52000140)
#define PWR_REG (*(volatile unsigned char *) 0x52000144)
#define EP_INT_REG (*(volatile unsigned char *) 0x52000148)
#define USB_INT_REG (*(volatile unsigned char *) 0x52000158)
#define EP_INT_EN_REG (*(volatile unsigned char *) 0x5200015C)
#define USB_INT_EN_REG (*(volatile unsigned char *) 0x5200016C)
#define FRAME_NUM1_REG (*(volatile unsigned char *) 0x52000170)
#define FRAME_NUM2_REG (*(volatile unsigned char *) 0x52000174)
#define INDEX_REG (*(volatile unsigned char *) 0x52000178)
#define MAXP_REG (*(volatile unsigned char *) 0x52000180)
#define EP0_CSR (*(volatile unsigned char *) 0x52000184)
#define IN_CSR1_REG (*(volatile unsigned char *) 0x52000184)
#define IN_CSR2_REG (*(volatile unsigned char *) 0x52000188)
#define OUT_CSR1_REG (*(volatile unsigned char *) 0x52000190)
#define OUT_CSR2_REG (*(volatile unsigned char *) 0x52000194)
#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *) 0x52000198)
#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *) 0x5200019C)
#define EP0_FIFO (*(volatile unsigned char *) 0x520001C0)
#define EP1_FIFO (*(volatile unsigned char *) 0x520001C4)
#define EP2_FIFO (*(volatile unsigned char *) 0x520001C8)
#define EP3_FIFO (*(volatile unsigned char *) 0x520001CC)
#define EP4_FIFO (*(volatile unsigned char *) 0x520001D0)
#define EP1_DMA_CON (*(volatile unsigned char *) 0x52000200)
#define EP1_DMA_UNIT (*(volatile unsigned char *) 0x52000204)
#define EP1_DMA_FIFO (*(volatile unsigned char *) 0x52000208)
#define EP1_DMA_TTC_L (*(volatile unsigned char *) 0x5200020C)
#define EP1_DMA_TTC_M (*(volatile unsigned char *) 0x52000210)
#define EP1_DMA_TTC_H (*(volatile unsigned char *) 0x52000214)
#define EP2_DMA_CON (*(volatile unsigned char *) 0x52000218)
#define EP2_DMA_UNIT (*(volatile unsigned char *) 0x5200021C)
#define EP2_DMA_FIFO (*(volatile unsigned char *) 0x52000220)
#define EP2_DMA_TTC_L (*(volatile unsigned char *) 0x52000224)
#define EP2_DMA_TTC_M (*(volatile unsigned char *) 0x52000228)
#define EP2_DMA_TTC_H (*(volatile unsigned char *) 0x5200022C)
#define EP3_DMA_CON (*(volatile unsigned char *) 0x52000240)
#define EP3_DMA_UNIT (*(volatile unsigned char *) 0x52000244)
#define EP3_DMA_FIFO (*(volatile unsigned char *) 0x52000248)
#define EP3_DMA_TTC_L (*(volatile unsigned char *) 0x5200024C)
#define EP3_DMA_TTC_M (*(volatile unsigned char *) 0x52000250)
#define EP3_DMA_TTC_H (*(volatile unsigned char *) 0x52000254)
#define EP4_DMA_CON (*(volatile unsigned char *) 0x52000258)
#define EP4_DMA_UNIT (*(volatile unsigned char *) 0x5200025C)
#define EP4_DMA_FIFO (*(volatile unsigned char *) 0x52000260)
#define EP4_DMA_TTC_L (*(volatile unsigned char *) 0x52000264)
#define EP4_DMA_TTC_M (*(volatile unsigned char *) 0x52000268)
#define EP4_DMA_TTC_H (*(volatile unsigned char *) 0x5200026C)
#endif// Watchdog Timer
#define WTCON (*(volatile unsigned long *) 0x53000000)
#define WTDAT (*(volatile unsigned long *) 0x53000004)
#define WTCNT (*(volatile unsigned long *) 0x53000008)// IIC
#define IICCON (*(volatile unsigned long *) 0x54000000)
#define IICSTAT (*(volatile unsigned long *) 0x54000004)
#define IICADD (*(volatile unsigned long *) 0x54000008)
#define IICDS (*(volatile unsigned long *) 0x5400000C)
#define IICLC (*(volatile unsigned long *) 0x54000010)// IIS
#define IISCON (*(volatile unsigned long *) 0x55000000)
#define IISMOD (*(volatile unsigned long *) 0x55000004)
#define IISPSR (*(volatile unsigned long *) 0x55000008)
#define IISFCON (*(volatile unsigned long *) 0x5500000C)
#define IISFIFO (*(volatile unsigned short*) 0x55000010)#ifdef __BIG_ENDIAN
#undef IISFIFO
#define IISFIFO (*(volatile unsigned short*) 0x55000012)
#endif// I/O port
#define GPACON (*(volatile unsigned long *) 0x56000000)
#define GPADAT (*(volatile unsigned long *) 0x56000004)#define GPBCON (*(volatile unsigned long *) 0x56000010)
#define GPBDAT (*(volatile unsigned long *) 0x56000014)
#define GPBUP (*(volatile unsigned long *) 0x56000018)#define GPCCON (*(volatile unsigned long *) 0x56000020)
#define GPCDAT (*(volatile unsigned long *) 0x56000024)
#define GPCUP (*(volatile unsigned long *) 0x56000028)#define GPDCON (*(volatile unsigned long *) 0x56000030)
#define GPDDAT (*(volatile unsigned long *) 0x56000034)
#define GPDUP (*(volatile unsigned long *) 0x56000038)#define GPECON (*(volatile unsigned long *) 0x56000040)
#define GPEDAT (*(volatile unsigned long *) 0x56000044)
#define GPEUP (*(volatile unsigned long *) 0x56000048)#define GPFCON (*(volatile unsigned long *) 0x56000050)
#define GPFDAT (*(volatile unsigned long *) 0x56000054)
#define GPFUP (*(volatile unsigned long *) 0x56000058)#define GPGCON (*(volatile unsigned long *) 0x56000060)
#define GPGDAT (*(volatile unsigned long *) 0x56000064)
#define GPGUP (*(volatile unsigned long *) 0x56000068)#define GPHCON (*(volatile unsigned long *) 0x56000070)
#define GPHDAT (*(volatile unsigned long *) 0x56000074)
#define GPHUP (*(volatile unsigned long *) 0x56000078)#define GPJCON (*(volatile unsigned long *) 0x560000D0)
#define GPJDAT (*(volatile unsigned long *) 0x560000D4)
#define GPJUP (*(volatile unsigned long *) 0x560000D8)#define MISCCR (*(volatile unsigned long *) 0x56000080)
#define DCLKCON (*(volatile unsigned long *) 0x56000084)
#define EXTINT0 (*(volatile unsigned long *) 0x56000088)
#define EXTINT1 (*(volatile unsigned long *) 0x5600008C)
#define EXTINT2 (*(volatile unsigned long *) 0x56000090)
#define EINTFLT0 (*(volatile unsigned long *) 0x56000094)
#define EINTFLT1 (*(volatile unsigned long *) 0x56000098)
#define EINTFLT2 (*(volatile unsigned long *) 0x5600009C)
#define EINTFLT3 (*(volatile unsigned long *) 0x560000A0)
#define EINTMASK (*(volatile unsigned long *) 0x560000A4)
#define EINTPEND (*(volatile unsigned long *) 0x560000A8)
#define GSTATUS0 (*(volatile unsigned long *) 0x560000AC)
#define GSTATUS1 (*(volatile unsigned long *) 0x560000B0)
#define GSTATUS2 (*(volatile unsigned long *) 0x560000B4)
#define GSTATUS3 (*(volatile unsigned long *) 0x560000B8)
#define GSTATUS4 (*(volatile unsigned long *) 0x560000BC)
#define MSLCON (*(volatile unsigned long *) 0x560000CC)// RTC
#ifdef __BIG_ENDIAN
#define RTCCON (*(volatile unsigned char *) 0x57000043)
#define TICNT (*(volatile unsigned char *) 0x57000047)
#define RTCALM (*(volatile unsigned char *) 0x57000053)
#define ALMSEC (*(volatile unsigned char *) 0x57000057)
#define ALMMIN (*(volatile unsigned char *) 0x5700005B)
#define ALMHOUR (*(volatile unsigned char *) 0x5700005F)
#define ALMDATE (*(volatile unsigned char *) 0x57000063)
#define ALMMON (*(volatile unsigned char *) 0x57000067)
#define ALMYEAR (*(volatile unsigned char *) 0x5700006B)
#define RTCRST (*(volatile unsigned char *) 0x5700006F)
#define BCDSEC (*(volatile unsigned char *) 0x57000073)
#define BCDMIN (*(volatile unsigned char *) 0x57000077)
#define BCDHOUR (*(volatile unsigned char *) 0x5700007B)
#define BCDDATE (*(volatile unsigned char *) 0x5700007F)
#define BCDDAY (*(volatile unsigned char *) 0x57000083)
#define BCDMON (*(volatile unsigned char *) 0x57000087)
#define BCDYEAR (*(volatile unsigned char *) 0x5700008B)#else //Little Endian
#define RTCCON (*(volatile unsigned char *) 0x57000040)
#define TICNT (*(volatile unsigned char *) 0x57000044)
#define RTCALM (*(volatile unsigned char *) 0x57000050)
#define ALMSEC (*(volatile unsigned char *) 0x57000054)
#define ALMMIN (*(volatile unsigned char *) 0x57000058)
#define ALMHOUR (*(volatile unsigned char *) 0x5700005C)
#define ALMDATE (*(volatile unsigned char *) 0x57000060)
#define ALMMON (*(volatile unsigned char *) 0x57000064)
#define ALMYEAR (*(volatile unsigned char *) 0x57000068)
#define RTCRST (*(volatile unsigned char *) 0x5700006C)
#define BCDSEC (*(volatile unsigned char *) 0x57000070)
#define BCDMIN (*(volatile unsigned char *) 0x57000074)
#define BCDHOUR (*(volatile unsigned char *) 0x57000078)
#define BCDDATE (*(volatile unsigned char *) 0x5700007C)
#define BCDDAY (*(volatile unsigned char *) 0x57000080)
#define BCDMON (*(volatile unsigned char *) 0x57000084)
#define BCDYEAR (*(volatile unsigned char *) 0x57000088)
#endif// A/D Converter
#define ADCCON (*(volatile unsigned long *) 0x58000000)
#define ADCTSC (*(volatile unsigned long *) 0x58000004)
#define ADCDLY (*(volatile unsigned long *) 0x58000008)
#define ADCDAT0 (*(volatile unsigned long *) 0x5800000C)
#define ADCDAT1 (*(volatile unsigned long *) 0x58000010)
#define ADCUPDN (*(volatile unsigned long *) 0x58000014) // SPI
#define SPCON0 (*(volatile unsigned long *) 0x59000000)
#define SPSTA0 (*(volatile unsigned long *) 0x59000004)
#define SPPIN0 (*(volatile unsigned long *) 0x59000008)
#define SPPRE0 (*(volatile unsigned long *) 0x5900000C)
#define SPTDAT0 (*(volatile unsigned long *) 0x59000010)
#define SPRDAT0 (*(volatile unsigned long *) 0x59000014)#define SPCON1 (*(volatile unsigned long *) 0x59000020)
#define SPSTA1 (*(volatile unsigned long *) 0x59000024)
#define SPPIN1 (*(volatile unsigned long *) 0x59000028)
#define SPPRE1 (*(volatile unsigned long *) 0x5900002C)
#define SPTDAT1 (*(volatile unsigned long *) 0x59000030)
#define SPRDAT1 (*(volatile unsigned long *) 0x59000034)// SD Interface
#define SDICON (*(volatile unsigned long *) 0x5A000000)
#define SDIPRE (*(volatile unsigned long *) 0x5A000004)
#define SDICARG (*(volatile unsigned long *) 0x5A000008)
#define SDICCON (*(volatile unsigned long *) 0x5A00000C)
#define SDICSTA (*(volatile unsigned long *) 0x5A000010)
#define SDIRSP0 (*(volatile unsigned long *) 0x5A000014)
#define SDIRSP1 (*(volatile unsigned long *) 0x5A000018)
#define SDIRSP2 (*(volatile unsigned long *) 0x5A00001C)
#define SDIRSP3 (*(volatile unsigned long *) 0x5A000020)
#define SDIDTIMER (*(volatile unsigned long *) 0x5A000024)
#define SDIBSIZE (*(volatile unsigned long *) 0x5A000028)
#define SDIDCON (*(volatile unsigned long *) 0x5A00002C)
#define SDIDCNT (*(volatile unsigned long *) 0x5A000030)
#define SDIDSTA (*(volatile unsigned long *) 0x5A000034)
#define SDIFSTA (*(volatile unsigned long *) 0x5A000038)
#define SDIIMSK (*(volatile unsigned long *) 0x5A00003C)
#define SDIDAT (*(volatile unsigned char *) 0x5A000040)#ifdef __BIG_ENDIAN
#undef SDIDAT
#define SDIDAT (*(volatile unsigned char *) 0x5A000043)
#endif// AC97 Audio-CODEC Interface
#define AC_GLBCTRL (*(volatile unsigned long *) 0x5B000000)
#define AC_GLBSTAT (*(volatile unsigned long *) 0x5B000004)
#define AC_CODEC_CMD (*(volatile unsigned long *) 0x5B000008)
#define AC_CODEC_STAT (*(volatile unsigned long *) 0x5B00000C)
#define AC_PCMADDR (*(volatile unsigned long *) 0x5B000010)
#define AC_MICADDR (*(volatile unsigned long *) 0x5B000014)
#define AC_PCMDATA (*(volatile unsigned long *) 0x5B000018)
#define AC_MICDATA (*(volatile unsigned long *) 0x5B00001C)// Exception vector
#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xc))
#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1c))
// Interrupt vector
#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2c))
#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
#define pISR_CAM (*(unsigned *)(_ISR_STARTADDRESS+0x38)) // Added for 2440.
#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3c))
#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
#define pISR_WDT_AC97 (*(unsigned *)(_ISR_STARTADDRESS+0x44)) //Changed to pISR_WDT_AC97 for 2440A
#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4c))
#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5c))
#define pISR_LCD (*(unsigned *)(_ISR_STARTADDRESS+0x60))
#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6c))
#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
#define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74))
#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78))
#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7c))
#define pISR_NFCON (*(unsigned *)(_ISR_STARTADDRESS+0x80)) // Added for 2440.
#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8c))
#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0x9c))// Interrupt Pending Bit
#define BIT_EINT0 (1 << 0)
#define BIT_EINT1 (1 << 1)
#define BIT_EINT2 (1 << 2)
#define BIT_EINT3 (1 << 3)
#define BIT_EINT4_7 (1 << 4)
#define BIT_EINT8_23 (1 << 5)
#define BIT_CAM (1 << 6)
#define BIT_nBAT_FLT (1 << 7)
#define BIT_TICK (1 << 8)
#define BIT_WDT_AC97 (1 << 9)
#define BIT_TIMER0 (1 << 10)
#define BIT_TIMER1 (1 << 11)
#define BIT_TIMER2 (1 << 12)
#define BIT_TIMER3 (1 << 13)
#define BIT_TIMER4 (1 << 14)
#define BIT_UART2 (1 << 15)
#define BIT_LCD (1 << 16)
#define BIT_DMA0 (1 << 17)
#define BIT_DMA1 (1 << 18)
#define BIT_DMA2 (1 << 19)
#define BIT_DMA3 (1 << 20)
#define BIT_SDI (1 << 21)
#define BIT_SPI0 (1 << 22)
#define BIT_UART1 (1 << 23)
#define BIT_NFCON (1 << 24)
#define BIT_USBD (1 << 25)
#define BIT_USBH (1 << 26)
#define BIT_IIC (1 << 27)
#define BIT_UART0 (1 << 28)
#define BIT_SPI1 (1 << 29)
#define BIT_RTC (1 << 30)
#define BIT_ADC (1 << 31)
#define BIT_ALLMSK (0xFFFFFFFF)#define BIT_SUB_RXD0 (1 << 0)
#define BIT_SUB_TXD0 (1 << 1)
#define BIT_SUB_ERR0 (1 << 2)
#define BIT_SUB_RXD1 (1 << 3)
#define BIT_SUB_TXD1 (1 << 4)
#define BIT_SUB_ERR1 (1 << 5)
#define BIT_SUB_RXD2 (1 << 6)
#define BIT_SUB_TXD2 (1 << 7)
#define BIT_SUB_ERR2 (1 << 8)
#define BIT_SUB_TC (1 << 9)
#define BIT_SUB_ADC_S (1 << 10)
#define BIT_SUB_CAM_C (1 << 11)
#define BIT_SUB_CAM_P (1 << 12)
#define BIT_SUB_WDT (1 << 13)
#define BIT_SUB_AC97 (1 << 14)
#define BIT_SUB_ALLMSK (0x000007FF)#define ClearPending(bit) { SRCPND = bit; \INTPND = INTPND; }#endif // __S3C2440_H三、编译，烧录，打开串口助手，接收到数据。
工程源码下载
Keil5 平台 S3C2440裸机程序开发-----中断系统/UART相关推荐
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