Allegro DFM Ravel Rule检查工具介绍

Allegro任何一个版本都支持DFM Ravel Rule检查，即便是166的版本
打开后的界面如下所示

可以检查项目
测试点，阻焊，走线，丝印，过孔，milling，装配，outline相关的DFM检查
可以让违反规则的设计处以DRC的形式报出来
避免加工问题
首先介绍如何打开这个工具

软件在默认的情况下是无法打开这个工具，需要添加一个用户环境变量
如下图

DFM_RAV_PATH
D:\Cadence\SPB_16.6\share\pcb\dfm_ravel
这是软件安装路径
2. 切换was performance editor

打开DFM RAVEL界面

工具就启动成功了

工具同时支持调入一个设置好的规则，点击Rule调入规则
Clear CM可以清除已经设置好的规则

This section is describe what the function allegro have ,helpfully could let user know more about allegro
Allegro Design and Analysis includes design authoring
PCB layout and Library and Design Data Management
With. It can ensure the end-to-end design of PCB with high quality and efficiency
Realize smooth data transfer between tools, shorten PCB design cycle, and shorten product
Market time

Design authoring
Provide a flexible logic constraint driven flow, management design rules, network hierarchy,
Bus and differential pair.
1.1.1 Main features and functions
Through hierarchical and design “derivation” function, improve the original of complex design
Map editing efficiency.
Powerful CIS helps users quickly determine part selection and accelerate design flow
And reduce project cost.
1.2.1 Main features
Schematic designers and PCB design engineers can work in parallel.
Advanced design efficiency improves functions, such as copying the previous schematic design Select multiplexing with or by page.
Seamless integration into pre simulation and signal analysis.
1.2.2 Main Functions
Provide schematic diagram and HDL/Verilog design input.
Assign and manage high-speed design rules.
Support netclasses, buses, extension networks and differential pairs.
Powerful library creation and management functions.
Allows synchronization of logical and physical designs.
Realize multi-user parallel development and version control.
Pre integration simulation and signal analysis.
Support customizable user interface and enterprise customization development.
1.3 o Allegro n Design Publisher
1.3.1 Main Features and Functions
Allows you to share designs with others using PDF files.
The entire design is represented in a single, compact PDF format.
Improve design readability.
Provide content control - users can select the content to be published.
1.4 Allegro A FPGA m System Planner
1 1.4.1 Main features and functions
Complete and scalable FPGA/PCB collaborative design technology for ideal "
Design and correct "pin assignment.
Scalable FPGA/PCB protocol from OrCAD Capture to Allegro GXL
Same as the design solution.
Shorten the optimization pin allocation time and accelerate the PCB design cycle.
B PCB layout
It provides expandable and easy to use PCB design (including RFPCB)
Then drive PCB design solution. It also includes innovative new automatic delivery
Mutual technology can effectively improve the wiring of high-speed interfaces; Apply EDMD (IDX) mode, which makes ECAD/MCAD work smoothly; Execute modern industry standard IPC-2581,
Ensure that the design data is simply and high-quality transferred to the downstream link.
2.1.1 Main features
Speed up the design process from layout, wiring to manufacturing.
Including powerful functions, such as design zoning, RF design functions and global design rules Stroke.
It can improve productivity and help engineers to quickly move up to mass production* g- M4 G8 |6 }9 k7 G
2.1.2 Main Functions
Provide scalable full function PCB design solutions.
Enable constraint driven design processes to reduce design iterations.
Integrated DesignTrueDFM technology provides real-time DFM inspection.
Provide a single, consistent context for management.
Minimize design iterations and reduce overall Flex and rigid flexible design
Cost, and has advanced rigid and flexible design functions.
Realize dynamic concurrent team design capability, shorten design cycle, and greatly reduce
Time spent in routing, winding and optimization.
Provide integrated RF/analog design and mixed signal design environment.
Provides interactive layout and component placement.
Provide design partitions for large distributed development teams.
Realize real-time, interactive push editing of routing.
It is allowed to use dynamic copper sheet technology to edit and update in real time.
Manage netscheduling, timing, crosstalk, routing by designated layer and area Bundle.
Provide proven PCB routing technology for automatic routing.
Realize hierarchical route planning and accelerate the completion of design.
Shorten interconnect planning and cabling time for high-speed interface intensive design.
Provide a comprehensive, powerful and easy-to-use tool suite to help designers
Efficient and successful manufacturing switch: DFM Checker is aimed at the company/manufacturer
Review the specific rules of manufacturing partners; Used to reduce manufacturing and assembly documents
The document editing time of the file can reach 70%; The panel editor will assemble the panel design
The intention is communicated to the manufacturing partners; Output design data in various manufacturing formats.
y Library d and n Design a Data Management
For cost-effective projects that need to be delivered on time, it is easy to obtain
Current component information and design data are critical. library and design
Data management is a collaborative control of the company’s internal cooperation and design process
Advanced functions are provided. As the design cycle shortens and the complexity increases, you
There must be a design approach that increases predictability and accelerates design turnaround.
3.1.1 Main features
Reduce time and optimize library development related resources.
Improve the precision in the process of parts manufacturing. Q9 b
3.1.2 Main functions
Reduce time and optimize library development and validation through integrated creation and validation processes Certification related resources.
A simple method to develop devices with large pin count can shorten the time from a few days to A few minutes.
Powerful graphic editor supports custom shape and spreadsheet import for
Schematic symbols are created to ensure the reliability and integrity of data.
Supports the import of part information from general industry formats, allowing rapid creation and Update part information.
Common library development environment supporting schematic tools from different suppliers, including Mentor Graphics Design Architect and Mentor Graphics Viewdraw。
Built in version management is provided through metadata support.
Reduce errors through real-time and batch validation of part data.
And Cadence OrCAD® Capture, Allegro PCB Design Editor
HDL, Allegro Package Designer and Allegro EDM are tightly integrated.
3.2.1 Main features
Provide a common library and design data interface for all members of the design team.
Expand access and visibility to component information, design data, and tools.
Simplify part selection through parametric component browsing.
3.2.2 Main Functions
Eliminate redundant component inputs and input errors.
Reduce the number of Engineering Change Orders (ECOs) for different or obsolete libraries.
Automatically notify engineers of changes to standard parts in active/archived designs.
List of parts to control bulk procurement and compliance.
3.3.1 Main features
Create new standards compliant libraries in a short time.
Realize the dream of unified component library by synchronizing your ECAD and MCAD libraries.
Quickly and easily rebuild libraries for different technologies.
3.3.2 Main Functions
Automatically generate encapsulation from templates and existing 3D models.
The rule and template editor can be customized.
Local support for MCAD3D models.
Verify ECAD footprints through 3D models to improve the accuracy of the library.
Use automatic search and coordinate system alignment to expand from the repository with 3D mode
The existing ECAD library for the.
Support to copy PTCCreo, Siemens NX MCAD for other MCAD suppliers
Library and STEP.
Reuse existing library models in future design to reduce design time.
Create different libraries for different standards (flex, HDI and different welding processes)
It only takes a few days, not months.
Ensure the accuracy and integrity of the library through automatic inspection and verification

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