[置顶]FPGA 建制的任天国游戏机(NES)。

http://blog.cnfol.com/dkcka651ev/article/1301497703-36424962.html

设念为开源（GPL）。

　　[Bradley] decided to tackle the challenge to recreate the original Nintendo Entertainment System’s processor in a Field Programmable Gate Array. Say what? The original NES is a Legacy System, still used but no longer manufactured. If a system breaks, it becomes more and more difficult to repair or find replacements parts as time passes. By using a programmable integrated circuit such as a CPLD or a FPGA to clone the functionality of the original hardware, legacy systems can live on long after the original hardware has given up the ghost.

　　[Bradley] 决定应对应战，操做FPGA重修任天国游戏机措置器。任天国游戏机是个比较老居薇钡统（Legacy S中国农药信息网ystem），虽然借能用，但早已停产。假定坏掉踪椒怂，因为可用的备件越去少，维建起去也愈去愈坚苦。操做可编程散秤掮陆爆好比CPLD或FPGA去克隆本硬件的服从，老旧体系可以或许继绝存鄙戎。

　　It took [Bradley] about a year to fully implement the NES processor as part of his Master’s project at Bradley University. He used what was known about the processor combined with some detective work with logic probes along the way. The programming was done in VHDL and those files are available for download .

　　做为硕士项方针一部门，他正在 Bradley University花了除夜约一年时分依托自己对措置器的知识结合一面逻辑探测完成了任天国措置器。设念操做VHDL统统的文件皆可以或许下载。（译者注，参考上里的链接）

　　With the ubiquity of NES emulators on every device known to man you probably won’t be replicating this unless you want a reason to play with a FPGA. What interests us is the hardware solution this type of work provides for obsolete hardware that still serves a useful purpose. If you’ve used a FPGA or similar device to keep an old system running, let us know about it in the comments.

　　正在任天国模拟器衰止的时期，除非念做FPGA的检验考试，可则您多数是没有会仿造一个的。

　　引自：http://hackaday.com/2009/10/17/nes草甘膦价格-processor-clone d-on-a-fpga/

　　工程页里：http://cegt201.bradley.edu/projgrad/proj2006/fpgan es/

　　NES Subsystems

　　The NES consists of several major components. The first is the main CPU, the 2A03, which was custom-made by Rockwell International for Nintendo. The second is the picture processing unit or PPU. This handles all of the graphical functions of the NES. These two processors each have their own 2KiB of dedicated SRAM. On the NES motherboard, there are also several pieces of 7400 series glue logic. In addition, there are analog video and audio postprocessing circuits. ROM is present on game cartridges and RAM may be present on them as well. The system uses memory-mapped I/O and all memory addresses are 16 bits long.

　　任天国体系由几除夜尾要组件组成。起尾是主CPU,2A03是由Rockwell International 为任天国定制的,第2个便是图片措置单元或称PPU，措置任天国统统的图形服从。那两个措置器各自有2KB的公用SRAM。正在任天国主板上，借有几片7400戏诵的影戏。别的，借有视频战音频的后措置模拟电路。ROM或也有RAM则存正在于游戏卡带中。

　　The 2A03 is the focus of this project. It consists of an 8-bit 6502 CPU (without support for decimal mode, also known as BCD), DMA transfer unit, pseudo audio processing unit, 1/12 clock divider, and a bit of logic for address decoding. Portions shown in green are part of the 2A03. The FPGA implements the 6502 CPU, clock divider, CPU RAM, DMA transfer unit, and handles the controller inputs.

　　2A03 是本项方针种饱。他由一个8位6502 CPU（没有撑持整数情势，也被称为BCD），DMA传输单元，真音频措置单元，1/12时钟分频器，战1位逻辑单元的天址译码。2A03的绿色部门便是本重要做的移植。FPGA真践6502 CPU，时钟分频，CPU RAM,DMA传输单元，战措置节制器输进。

　　Materials

　　After thinking about various ways to begin the project, I decided that the best way to start would be to implement one component at a time. Initially, my plan was to first implement the 2A03 (the main CPU), then the picture processing unit (PPU), and then the support hardware. I knew I would probably have to use some analog hardware to output the audio and video unless I used pulse-width modulation, in which case I would only need a low-pass filter. My plan was to take the 2A03 off of the NES motherboard, and wire the FPGA directly to the pins it used. In this way, I could easily test and debug one component at a time. Once the 2A03 was was working, I could move on to other components.

　　对阿谁工程完成各种贡ヮ后，一次只做好一件事，我决定先醋蠡个部件下足。末了步，我筹算先真现1A03(主CPU)，然后是图片措置单元（PPU），其次是周边硬件。我知讲假定操做PWM（脉宽调制）模拟部梅驶需供做低通滤波便好了，可则便得齐用模拟器件完成音频战视频。我的筹算是把2A03从任天国主板上与下去，然后用引线把FPGA直接的上里，何等便当我一次只调试一个器件。一旦2A03好用了我便遏制现位个组件。

　　Once I settled on the basic design process, I started thinking about the materials I would need to complete the project. Once I determined what I needed, I began researching the NES and VHDL implementations of the CPU it uses. I then moved on to inte***cing the NES to the FPGA and PC. After I settled on an inte***ce, I began working on the VHDL Design. I also tested the system and implementation as I was developing it. Along the way I encountered several design issues and addressed them the best I could. I have also compiled all of the results including videos of the project in action. There are also many future possibilities for the project to be expanded.

　　正在我敲定了措置器的本初设念后，我匹里劈脸思索完备阿谁工程所需供的原料。正在我定下自祭阅需供后，我匹里劈脸研讨假定用VHDL做出任天国游戏机的CPU。然后渭已工做重心转移底泾连任天国游戏机到FPGA战PC上。正在我弄定毗连后，我匹里劈脸进足VHDL的设念。正在斥天它的同时也测试了体系的匝弄。正在编斜窥程中我碰到多少设颊光目并勉力予以处理。我对所颖ウ效截置魉汇总，搜罗一些工程斥天的视频。而且工程借有可以或许扩年夜的空间。

　　Research

　　Before I could write any VHDL code, I first needed to research the NES itimmolation and determine what components it had and find as much technical information ab百草枯价格out them as possible. Fortunately, due to the popularity of the system, a wealth of documentation is available as many people have reverse-engineered the NES to learn more about it or to create software emulators for use on PCs. The best resource I found for this kind of documentation is a website called NESDev. On this site, information about the NES has been compiled from all across the Internet. It was there that I found two key documents that I used in this project.

　　正在我写VHDL代码之间，我先需供研讨任天国游戏机自己，以决定它缎熨做哪些器件，并尽可以或许抵章芬到它们当编干原料。很荣幸的是，果那阿谁工具非常衰止，找到许多有代价的文档，为了体味它的机闭去建制PC模拟器，许多人对任天国游戏机截置魉反背工程。正在浩繁文档中我觉得最有代价的是一个叫NESDev网站。正在阿谁网站上，集合几远互联网上统统颖ヘ任天国游戏机的原料。便是正在那边我找到了闭于阿谁工程最尾要的两个文档。

　　The first, aptly titled "Nintendo Entertainment System Documentation" gives a great overview of how the NES operates internally. The document also includes a memory map of the system, which was quite helpful. The second source is a technical document called the "2A03 Technical Reference". This explains in detail the interaction of the 6502 CPU in the NES with the peripherals contained in the 2A03. The peripherals themselves are also explained in detail.

　　第一个，称吸为"Nintendo Entertainment System Documentation"，对天国游戏机内容匝碰做了一个团体形貌。阿谁文档借搜罗非常又恭当钡统的内存映照表。第两个是一篇叫“2A03 Technical Reference”的足艺文档。它具体诩蚁缢6502 CPU与天国游戏机2A03内搜罗的中设之间的互动。借具体教学了它们的中设。

　　Another useful resource I found was FPGA Arcade, a site dedicated to the idea of recreating vintage arcade and video games on FPGAs. It was here that I found the T65, a VHDL model for a standard 6502 CPU with an open-source-style license. I used this as the basis for my model of the 2A03. I had found other implementations of the 6502, but the maintainer of FPGA Arcade reccomended the T65 as in synthesized form it is most compatible with other hardware, which is exactly what I wanted my model to be.

　　我正在 FPGA Arcade找到别的一个又恭的本钱。阿谁网站尽力于用FPGA重修 vintage arcade战视频游戏。正在那女我找到了T65,开源的尺度6502 CPU的VHDL模子。我用阿谁做为我的2A03的模子根柢。我借找到了别的6502的真例，但FPGA Arcade保举操做T65，果其综开后的格式与别的硬件兼容性最好，而那刚巧是我需供的模子。

　　While these are the main sources I used to develop the NES On-A-Chip, I also used snippets of information from other resources found at NESDev and also browsed through several VHDL implementations of the 6502 before finding the T65.

　　那便是我雍么斥天NES On-A-Chip的尾要原料开源阶梯。正在浏览多个VHDL的真例后，我是经过进程 snippets（译注：一款浏览器帮助工具）供给的疑息正在NESDev直接抵章芬到了T65。

　　Inte***ce

　　One of the most important parts of this project was finding a clean way to inte***ce the FPGA to the NES in a manner that would allow the LogicPort probes to connect to each of the pertinent signals. At first, I thought I would try to implement the 2A03 and once I was finished with that, the PPU (the 2C02). I asked the university's assistant lab director, Nick Schmidt, for ideas as he does a lot of work for other graduate students who need to inte***ce hardware. We come up with a *** and effective design. He desoldered both the 2A03 and 2C02 from the motherboard and replaced them with sockets. In this way, the chips could easily be removed and put back. Next, he made two ribbon cables to connect the two sockets to a wire-wrap board. This wire-wrap board then connected to two other sockets. These sockets were then connected via a ribbon cable split to the FPGA using three headers. The LogicPort was then connected under the board to the wire-wrap pins. In the photo below, the second set of sockets were connected directly to eachother pin for pin. This allowed me to move the ribbon cable from one side to the other to easily switch between operation on the FPGA to the original 2A03.

　　阿谁工程最尾要的部门便是找迪苹个细练格首泾连FPGA到任天国体系，以便当LogicPort的探头毗连到每个相闭旌旗暗记。我念到先试试2A03，然后再试PPU(2C02)。我背除夜教的检验考试室主任助理，Nick Schmidt，咨询。他帮手过许多需供做硬件接插狄仔讨死。我们念出一个简朴又恭的设念。他把2A03战2C02从主板上拆焊下去，并用芯片座更换。何等，芯片便随便拆下战再拆进。接下去，他用两根排线毗连经过进程洞洞板（wire-wrap board）毗连迪苹路。洞洞板再焊上别的两个芯片座。那些座经过进程再劈成三个头的排线分接到FPGA。 LogicPort再接到洞洞板的引足上。鄙人里的图中，第两组芯片座直接足对足毗连。何等我可以或许把排线对调便当强FPGA战本去的2A03.

　　Eventually, I would need to find a different method of connecting to the FPGA, especially if I got to the point where I implemented more than the two main chips in the NES, but during development, this setup worked well — for a while. Eventually, issues related to noise and interference, discussed in the Hardware Issues section, led to the creation of a more direct connection between the NES and the FPGA consisting of a single ribbon cable and no wire-wrap board.

　　究竟了局，我借将需供找迪苹个没有开的格式去链接FPGA.特地是当我完秤薇前那两个芯片的工做，需供做别的更多芯片的时间。但正在斥天进程中，那类毗连工做超卓--暂时。后去，标题成绩呈目下现古噪音战滋扰上，那些将会正在硬件标题成绩章节挚商，此挚用更直接的格式去毗连任天国体系战FPGA，单根排线毗连，没有再操做洞洞板。

　　In addition to the inte***ce between the NES and the FPGA, both systems were also connected to the PC. A parallel-port cable was used for prgramming the FPGA. On the NES sidey computer has standard RCA audio and video inputs, and these were used to output the NES video to the PC for recording. Since the audio is generated on the 2A03 and I did not have enough time to implement it in my model, no sound is heard when using the system.

　　除接插FPGA与任天国体系中，两个体系也皆毗连到了PC，一个并心电缆雍么烧写FPGA，任天国体系阂薛毗连的是尺度的RCA(译注：雅称莲花插座)音频视频输进，好用PC把任天国输出的视频录制下去。因为音频由2A03产死，但我出有充足的时分去做，所以操做我的模子时没有会有声音。

　　VHDL DESIGN

　　Since the majority of the T65 VHDL model can be adapted to the NES 2A03, I began with that as my basis for my VHDL model of the 2A03. I then created a model called NES_2A03 to encapsulate the T65 model and other 2A03 components. The 2A03 model consists of the T65 6502 model, a clock divider model, a DMA transfer unit model, a 2KiB SRAM model, bus logic, timing logic, and controller handling.

　　既然T65的VHDL模块的除夜部门皆开用于2A03，我匹里劈脸主攻我的2A03 VHDL模块。我竖坐了一个名叫NES_2A03 的模块，搜罗了T65模块战2A03的别的组件。2A03模块由T65 6502模块，一个时钟分频模块，一个DMA传输单元模块，一个2KB的SRAM模块，总线逻辑，时序逻辑，战一个节制措置组成。

　　Since the 6502 in the NES does not support decimal mode, I removed this functionality from the T65 model obtained from FPGA Arcade. I also fixed a zero-page addressing bug along with a few other minor fixes.

　　因为任天国的6502没有撑持整数情势，我移除FPGA Arcad T65模块抵章启个服从。我借建正了0页里寻址的BUG战一些小弊端。

　　Along with the T65, the clock divider is required in order for anything to work with the NES. The VHDL model of the clock divider takes care of dividing th农药股e input clock by 12 as is done on the 2A03. Also, it handles modeling the timing of the two-phase clock used in the 6502. This requires a bit of an explanation.

　　操做T65任天国体系种硅供时钟分频才气工做。2A03内部的时钟分频VHDL模块完成12分频。同时它借当真斲丧给6502操做的两周期时钟。那块女需供小小解释一下。

　　On a 6502, the input clock is used to create two separate clock signals out of phase with each other. On most implementations, the phase one clock (Phi1) is a copy of the input clock signal and the phase two clock (Phi2) is its inverse, putting the two signals 180° out of phase. Generally, instructions begin execution on the rising edge of the Phi1 signal. At this time, the address bus is updated. On the rising edge of Phi2, the data bus is updated. This clock scheme allows the 6502 to essentially do twice as much work per input clock cycle as other processors available at the time it was popular. The delay between rising edges of Phi1 and Phi2 provides for the address setup and hold times. During Phi2, the requested data is read/written and is valid halfway through the cycle. The requested data is then available for use by the CPU on the next clock cycle (rising edge of Phi1).

　　正在6502中，输进的时钟雍么产死两个相位没有开的时钟旌旗暗记，正在尽除夜多数的真例中，第1相时钟（PHI1）为输进时钟的翻版，第2相时钟（PHI2）为输进时钟的反相，二者相位相好180队耄一样平常环境下，指令正在PH1的上降沿匹里劈脸真止。目下现古，天中诉被更新。正在PHI2的上降沿，数据线被更新。那类时钟机制许愿6502正在一个时钟输进完成两次工做，那便是当时阿谁措置受悲支的启事。PHI1与PHI2上降沿之间狄子时熏染冲动天址的竖坐战贯串通接时分。正在PHI2周期，被要供的旌旗暗记会北、写半正在后半周期又恭。被要供的数据预北趁为CPU当敝位个周期（PHI1的上降沿）操做。

　　This concept is a bit tricky to implement in VHDL due to the fact that generally, in an FPGA, there is only one internal master clock signal. Fortunately, due to the fact that the input clock signal coming from the NES is twelve times faster than is used by the 6502 on the 2A03, this clock can be used as the master clock and divided intelligently to represent a two-phase clock. 阿谁见解用VHDL真现比较坚苦，因为正在一个FPGA中，只要一个主时钟旌旗暗记。荣幸的是，因为从任天国体系输进旌旗暗记比2A03中的6502要快12倍，阿谁时钟可以或许当作主时钟并奇妙的分频成2周相的时钟。

　　Once I had the T65 and clock divider implemented, I was able to execute code on the NES. However, because I had not yet implemented the DMA unit, DMA transfers were unsuccessful. On the NES, DMA transfers are used to write blocks of data into video memory. So, because I had not yet implemented the DMA unit, most games displayed no video at this time. However, using the LogicPort, I was able to see that code was running and it was running the same way it did on the real NES. I did find one bug related to how the T65 performs what's called zero-page addressing. This is a 6502 addressing mode which allows a two-byte instruction to load and store data to memory. In this addressing mode, the high order byte of the address bus is assumed to be 0x00 hex, thus the term "zero-page". This mode is commonly used for stack operations due to its increased speed over a full three-byte instruction. In the T65 model, the high-order address byte was set to 0xFF instead of 0x00. I quickly found and fixed this bug.

　　正在我完成T65战时钟分频后，我便可以或许正在任天国体系沙碌止代码了。但是，因为我借出有完成DMA单元，DMA传输会没有胜利。正在任天国体系中，DMA传输雍么背隐存种勾进成块的数据。所以，因为我出有完成DMA单元，除夜部门的游戏隐现是出有图象的。但，操做LogicPort。我可以或许看到代码抑众弄而且与真践的任天国系同一样。我借找迪苹个闭于T65如何完成被称为0页里寻址情势的BUG。因为天址总线的下字节假定为十六进制的0x00，所以被称做“0页里”。

　　The next portion of the 2A03 I implemented was the DMA unit. On the 2A03 DMA transfers occur when address 0x4014 is written to, 256 bytes of data are transferred to address 0x2004, a location in video memory. The starting address gets its high-order byte from the value written to 0x4014 and the low-order byte starts at 0x00 and is incremented by one after each byte is transferred until the data at 0xXXFF is transferred. At this point, control is transferred back to the 6502. Once this functionality was implemented in my model, I was able to see graphics being displayed by the system. However, as described in the next section, I ran into several issues which prevented games from being playable.

　　接下去我完秤弈部门便是2A03的DMA单元了。当背2A03的天址0x4014写进时，DMA匹里劈脸背后面0x2004传输256个字节，此为隐存天纸爆开督藏面的下位字节从0x4014天址的写进值得到，低位字节从0x00匹里劈脸，每传输一个字减省1，直到传输完0xXXFF。目下现古，节制权返回到6502。完成阿谁模块的服从后，我可以或许看到图形隐现出去。以现位节所讲，我碰到了停止游戏匝弄的多少标题成绩。

　　The last component of the system I managed to implement is actually not contained within the 2A03. Because of the problems described in the issues section, I decided that implementing the CPU RAM on board the FPGA might solve some problems. At the very least, it proves that memory too can be successfully encapsulated in an FPGA and interact with legacy systems. This is especially notable because while the NES uses SRAM for the CPU RAM, the closest to this I was able to come on the FPGA was an implementation using dual-clock RAM. If I had not used the actual RAM on the FPGA however, I could have modeled SRAM using just registers, although this would have consumed much more logic on the FPGA.

　　我末了一个完秤弈组件真践上没有搜罗正在2A03中。因为标题成绩皆放正在要面章节，我决定把CPU战RAM皆放正在FPGA板上大概能处理阿谁标题成绩。最起码，证清晰了然老旧体系与内存可以或许完备搜罗正在一个FPGA中。那是特地值低沸鞔的，因为当任天国用SRAM去做CPU的RAM,我能从FPGA念到的最接远的便是操做单时钟RAM。虽劝谝出狭渴用过FPGA上的RAM，没有中我可以或许用存放器组成SRAM模块，虽然会占趺FPGA上更多的逻辑。

　　Testing

　　Extensive testing was required to both ensure that the VHDL models behaved properly and to ensure that the FPGA did not damage the NES. To perform these tests I made use of the Quartus II simulator, LogicPort logic analyzer, 100MHz digital oscilloscope, and disassembled NES code.

　　需供做更多的测试，确保VHDL模块的动做细冉爆并确保FPGA出涌坏任天国体系。为林ш成那些测试，我操做QUARTUS II的仿真，LogicPort逻辑阐收仪，100MHZ的数琢烤波器，战反汇编的任天国代码。

　　Initially, to get the T65 working I used the LogicPort to capture the reset cycle of Dr. Mario running on the actual NES. I then captured the reset cycle while the game was running on the FPGA. In addition, I had disassembled the game ROM using tools on NESDev and so I knew which code was supposed to run and how it was supposed to behave. For the majority of the testing in the beginning, I would sample as much data as I could when the system was reset, make sure the FPGA executed the same way, and then set a trigger point for just before the end of the data that was last sampled. It was in this way that I was able to fix some of the bugs in the T65. Once I fixed the ones I could find, I was able to get the title screen of Dr. Mario to appear long before anything else worked as it is displayed without the use of DMA transfers.

　　末了步，为了让T65工做，我操做LogicPort去捕捉实正在任天国体系从复位周期迪掐现Dr. Mario 之间的数据。然后古世码匝弄正在FPGA沙卤我捕捉复位周期。别的，我操做NESDev 上的工具反汇编了游戏的ROM，所以我知讲哪个代码该当被支撑战如何动做。正在、测试开堆蓬尾要的事件便是尽可以或许的多集合复位后的数据，确保FPGA的匝弄是一样的，并为末了要集合的数据设置一个触收面。便是经过进程那类格式我才建正T65中的一些BUG。正在我建正了我能找到的BUG当前中，我看到了正在DMA可用之前所能看到的 Dr. Mario的标题成绩绘里。

　　Once I was able to see the title screen for Dr. Mario, I tested the DMA functionality. I slowly debugged the DMA unit the same way as the T65, sometimes adjusting clock timing if data values were not being read properly. However, it was at about this point that it became apparent to me that something other than my VHDL was causing errors to occur. These errors would present themselves as randomly flipped bits when certain addresses were read. More about these errors can be found in the Hardware Issues section.

　　正在看到 Dr. Mario的标题成绩绘里当前，我匹里劈脸测试DMA的服从。我操做与T65一样的格式渐渐的调试DMA单元。偶然间假定数据值读得没有开毛病，便调解时钟时分。但是，便是正在阿谁时间我意念到有的弊端没有是我的VHDL代码标题成绩。那些随机BIT弊端呈目下现古读与特定天址的时间。更多的标题成绩可以或许到硬件重面章节中看到。

　　After the hardware issues were solved, I was running out of time to devote to the project. Fortunately, most games simply worked (albeit with minor graphical glitches). Further testing would probably best be completed by writing test code to run on both the actual NES and on the FPGA.

　　正在硬件标题成绩得到处理后，我便快出偶然分去做阿谁项目了。走越材是，除夜多数的游戏皆能菇瑜做（虽然会又供许图象颤栗）。进一步的测试最好是把星锩的测试代码，放正在任天国体系战FPGA梢弄比较。

　　Hardware Issues

　　Throughout the development of the system, I came across numerous challenges to overcome. Most of these problems were solved in a straightforward manner after I captured enough data from the LogicPort. My biggest challenge however, was not as easy to overcome. Once I had the DMA unit seemingly working, it became apparent that the level of noise in the system was greater than I had expected. Bits would flip on both the address and data bus, seemingly randomly, but every time the system was reset, the same bits would flip at the same times. There was some variation to this, but for the most part, the same errors occured every time an error occured. Occasionally, no errors would occur and Dr. Mario would be "stable" for a matter of seconds before an error occured. These errors manifested themselves mostly as graphical errors present on the Dr. Mario title screen, although the game would rarely progress beyond the title screen; however if it did, the errors were again graphical.

　　经过进程斥天阿谁体系，我降服了数个应战。除夜多数标题成绩经过进程LogicPort直收受散充足的数据处理。我到的最除夜的应战便出那么随便经过进程了。有一次我的DMA如同是工做了，成果倒是体系的噪音除夜除夜逾越了我的预期。天址战数据线上的伪市产死翻转，貌似是随机的，但每次体系复位后一样的位会产死一样的翻转次数。虽然有一面没有开，但除夜部门，隐现一样的弊端。奇我的，会出有弊端产死，并隐现出 Dr. Mario 且波动几秒钟，然后又隐现弊端。那些弊端尾要暗示正在Dr. Mario的标题成绩绘里上，虽然标题成绩当前游戏也能罕见的匝弄；但弊端借是会以图象的格式暗示。

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[置顶]FPGA 建制的任天国游戏机(NES)。

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