Vivado pcie_can_bd.bd 代码
2024-04-18 01:46:58
版权声明：本文为博主原创文章，遵循 CC 4.0 BY-SA 版权协议，转载请附上原文出处链接和本声明。
本文链接：https://blog.csdn.net/qq_46621272/article/details/118249238?
PCIe TO CAN FPGA Vivado Block Design
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<bd:repository xmlns:bd="http://www.xilinx.com/bd" bd:BoundaryCRC="0x6F61C80873F099D5" bd:device="xc7a200tffg1156-2" bd:isValidated="true" bd:synthFlowMode="Hierarchical" bd:tool_version="2017.4" bd:top="pcie_can_bd" bd:version="1.00.a"><spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"><spirit:vendor>xilinx.com</spirit:vendor><spirit:library>BlockDiagram</spirit:library><spirit:name>pcie_can_bd</spirit:name><spirit:version>1.00.a</spirit:version><spirit:parameters><spirit:parameter><spirit:name>isTop</spirit:name><spirit:value spirit:format="bool" spirit:resolve="immediate">true</spirit:value></spirit:parameter></spirit:parameters><spirit:busInterfaces><spirit:busInterface><spirit:name>pcie_ref</spirit:name><spirit:slave/><spirit:busType spirit:library="interface" spirit:name="diff_clock" spirit:vendor="xilinx.com" spirit:version="1.0"/><spirit:abstractionType spirit:library="interface" spirit:name="diff_clock_rtl" spirit:vendor="xilinx.com" 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spirit:version="1.00.a"/></spirit:view></spirit:views><spirit:ports><spirit:port><spirit:name>pcie_rst_n</spirit:name><spirit:wire><spirit:direction>in</spirit:direction></spirit:wire></spirit:port><spirit:port><spirit:name>pcie_irq</spirit:name><spirit:wire><spirit:direction>in</spirit:direction></spirit:wire></spirit:port><spirit:port><spirit:name>axi_clk</spirit:name><spirit:wire><spirit:direction>out</spirit:direction></spirit:wire></spirit:port><spirit:port><spirit:name>axi_rstn</spirit:name><spirit:wire><spirit:direction>out</spirit:direction></spirit:wire></spirit:port></spirit:ports></spirit:model></spirit:component><spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"><spirit:vendor>xilinx.com</spirit:vendor><spirit:library>BlockDiagram</spirit:library><spirit:name>pcie_can_bd_imp</spirit:name><spirit:version>1.00.a</spirit:version><spirit:componentInstances><spirit:componentInstance><spirit:instanceName>xdma_0</spirit:instanceName><spirit:componentRef spirit:library="ip" spirit:name="xdma" spirit:vendor="xilinx.com" spirit:version="4.0"/><spirit:configurableElementValues><spirit:configurableElementValue spirit:referenceId="bd:xciName">pcie_can_bd_xdma_0_0</spirit:configurableElementValue><spirit:configurableElementValue spirit:referenceId="axilite_master_en">true</spirit:configurableElementValue><spirit:configurableElementValue spirit:referenceId="pf0_msi_enabled">false</spirit:configurableElementValue><spirit:configurableElementValue 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spirit:referenceId="C_PRH0_ADDR_TH">10000</spirit:configurableElementValue><spirit:configurableElementValue spirit:referenceId="C_PRH0_ADDR_TSU">10000</spirit:configurableElementValue><spirit:configurableElementValue spirit:referenceId="C_PRH0_BUS_MULTIPLEX">1</spirit:configurableElementValue><spirit:configurableElementValue spirit:referenceId="C_PRH0_DWIDTH_MATCH">1</spirit:configurableElementValue><spirit:configurableElementValue spirit:referenceId="C_PRH0_DWIDTH">8</spirit:configurableElementValue><spirit:configurableElementValue spirit:referenceId="C_PRH0_AWIDTH">8</spirit:configurableElementValue></spirit:configurableElementValues></spirit:componentInstance><spirit:componentInstance><spirit:instanceName>util_ds_buf_0</spirit:instanceName><spirit:componentRef spirit:library="ip" spirit:name="util_ds_buf" spirit:vendor="xilinx.com" spirit:version="2.1"/><spirit:configurableElementValues><spirit:configurableElementValue spirit:referenceId="bd:xciName">pcie_can_bd_util_ds_buf_0_0</spirit:configurableElementValue><spirit:configurableElementValue spirit:referenceId="C_BUF_TYPE">IBUFDSGTE</spirit:configurableElementValue></spirit:configurableElementValues></spirit:componentInstance></spirit:componentInstances><spirit:interconnections><spirit:interconnection><spirit:name>xdma_0_M_AXI_LITE</spirit:name><spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="axi_epc_0"/><spirit:activeInterface spirit:busRef="M_AXI_LITE" spirit:componentRef="xdma_0"/></spirit:interconnection></spirit:interconnections><spirit:adHocConnections><spirit:adHocConnection><spirit:name>pcie_rst_n_1</spirit:name><spirit:externalPortReference spirit:portRef="pcie_rst_n"/><spirit:internalPortReference spirit:componentRef="xdma_0" spirit:portRef="sys_rst_n"/></spirit:adHocConnection><spirit:adHocConnection><spirit:name>util_ds_buf_0_IBUF_OUT</spirit:name><spirit:internalPortReference spirit:componentRef="util_ds_buf_0" spirit:portRef="IBUF_OUT"/><spirit:internalPortReference spirit:componentRef="xdma_0" spirit:portRef="sys_clk"/></spirit:adHocConnection><spirit:adHocConnection><spirit:name>pcie_irq_1</spirit:name><spirit:externalPortReference spirit:portRef="pcie_irq"/><spirit:internalPortReference spirit:componentRef="xdma_0" spirit:portRef="usr_irq_req"/></spirit:adHocConnection><spirit:adHocConnection><spirit:name>xdma_0_axi_aclk</spirit:name><spirit:internalPortReference spirit:componentRef="xdma_0" spirit:portRef="axi_aclk"/><spirit:externalPortReference spirit:portRef="axi_clk"/><spirit:internalPortReference spirit:componentRef="axi_epc_0" spirit:portRef="s_axi_aclk"/></spirit:adHocConnection><spirit:adHocConnection><spirit:name>xdma_0_axi_aresetn</spirit:name><spirit:internalPortReference spirit:componentRef="xdma_0" spirit:portRef="axi_aresetn"/><spirit:externalPortReference spirit:portRef="axi_rstn"/><spirit:internalPortReference spirit:componentRef="axi_epc_0" spirit:portRef="s_axi_aresetn"/></spirit:adHocConnection></spirit:adHocConnections><spirit:hierConnections><spirit:hierConnection spirit:interfaceRef="pcie_ref/pcie_ref_1"><spirit:activeInterface spirit:busRef="CLK_IN_D" spirit:componentRef="util_ds_buf_0"/></spirit:hierConnection><spirit:hierConnection spirit:interfaceRef="epc/axi_epc_0_EPC_INTF"><spirit:activeInterface spirit:busRef="EPC_INTF" spirit:componentRef="axi_epc_0"/></spirit:hierConnection><spirit:hierConnection spirit:interfaceRef="pcie_mgt/xdma_0_pcie_mgt"><spirit:activeInterface spirit:busRef="pcie_mgt" spirit:componentRef="xdma_0"/></spirit:hierConnection></spirit:hierConnections></spirit:design><spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"><spirit:vendor>xilinx.com</spirit:vendor><spirit:library>Addressing/xdma_0</spirit:library><spirit:name>xdma</spirit:name><spirit:version>4.0</spirit:version><spirit:busInterfaces><spirit:busInterface><spirit:name>M_AXI</spirit:name><spirit:master><spirit:addressSpaceRef spirit:addressSpaceRef="M_AXI"/></spirit:master><spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/><spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/></spirit:busInterface><spirit:busInterface><spirit:name>M_AXI_LITE</spirit:name><spirit:master><spirit:addressSpaceRef spirit:addressSpaceRef="M_AXI_LITE"/></spirit:master><spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/><spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/></spirit:busInterface></spirit:busInterfaces><spirit:addressSpaces><spirit:addressSpace><spirit:name>M_AXI</spirit:name><spirit:range>16E</spirit:range><spirit:width>32</spirit:width><spirit:segments/></spirit:addressSpace><spirit:addressSpace><spirit:name>M_AXI_LITE</spirit:name><spirit:range>4G</spirit:range><spirit:width>32</spirit:width><spirit:segments><spirit:segment><spirit:name>SEG_axi_epc_0_PRH0</spirit:name><spirit:displayName>/axi_epc_0/S_AXI_MEM/PRH0</spirit:displayName><spirit:addressOffset>0x00020000</spirit:addressOffset><spirit:range>4K</spirit:range></spirit:segment></spirit:segments></spirit:addressSpace></spirit:addressSpaces></spirit:component></bd:repository>连接：采用 FPGA 实现 ＜PCIe to CAN＞ 网卡的设计 https://blog.csdn.net/qq_46621272/article/details/118242161?
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