//#define CODEC_SLAVE 1#if defined (CODEC_SLAVE) //imx6q:master, codec:slave{/** Note that bits [20:19] are defined differently by the i.MX6 Quad/Dual compared to the i.MX6 DualLite/Solo* The i.MX6 Solo/DualLite use bits 20:19 to control a PLL post-divider, whereas the Quad/Dual use bits 20:19* for testing purposes.*/#define PLL_AUDIO_CTRL_POST_DIV_1            (0x3 << 19)#define PLL_AUDIO_CTRL_BYPASS              (1 << 16)#define PLL_AUDIO_CTRL_ENABLE                (1 << 13)#define PLL_AUDIO_CTRL_POWERDOWN         (1 << 12)#define PLL_AUDIO_CTRL_MFI_MASK              (0x7F << 0)   /* In the docs these bits are labeled DIV_SELECT */#define CCM_ANALOG_PLL_AUDIO_CTRL                0x70#define CCM_ANALOG_PLL_AUDIO_CTRL_SET           0x74#define CCM_ANALOG_PLL_AUDIO_CTRL_CLR           0x78#define CCM_ANALOG_PLL_AUDIO_NUM                0x80#define CCM_ANALOG_PLL_AUDIO_DENOM              0x90//This register contains the numerator (A) of Audio PLL fractional loop divider.out32(MX6X_ANATOP_BASE + CCM_ANALOG_PLL_AUDIO_NUM, 0x2a0);//This register contains the Denominator (B) of Audio PLL fractional loop dividerout32(MX6X_ANATOP_BASE + CCM_ANALOG_PLL_AUDIO_DENOM, 0x3e8);//The control register provides control for the audio PLL.//This field controls the pll loop divider. Valid range for DIV_SELECT divider value: 27~54.out32(MX6X_ANATOP_BASE + CCM_ANALOG_PLL_AUDIO_CTRL_CLR, PLL_AUDIO_CTRL_MFI_MASK);//DIV_SELECT = 28 POST_DIV_SELECT = 0x3out32(MX6X_ANATOP_BASE + CCM_ANALOG_PLL_AUDIO_CTRL_SET, (0x1c & PLL_AUDIO_CTRL_MFI_MASK) | PLL_AUDIO_CTRL_POST_DIV_1);/* Power up and enable Audio PLL (PLL4) */out32(MX6X_ANATOP_BASE + CCM_ANALOG_PLL_AUDIO_CTRL_CLR, PLL_AUDIO_CTRL_BYPASS | PLL_AUDIO_CTRL_POWERDOWN);out32(MX6X_ANATOP_BASE + CCM_ANALOG_PLL_AUDIO_CTRL_SET, PLL_AUDIO_CTRL_ENABLE);/* the clock frequence of ssi2 is 12.288MHz*/init_ssi2_clk();init_audiomux(2, 3);}#else //imx6q:slave, codec:master{init_audiomux(3, 2);}#endif

该代码配置了SSI模块需要的工作时钟，但是配置完此之后，ssi仍然不能正常工作，主要是由于IMX6存在有门时钟