module fifo_sync(input           clk         ,input          rst_n       ,input  [7:0]   datain      ,  //输入数据input          wr          ,  //写请求input           rd          ,  //读请求output  reg [7:0]   dataout     ,  //输出数据output         empt        ,  //空标志output          full           // 满标志
);//定义寄存器
reg     [3:0]       cnt;  //计数器用于计算FIFO中存放了多少数据，方便提供满空标志
reg     [3:0]       wr_ptr, rd_ptr;  //读写指针
reg     [7:0]       fifo_mem    [15:0];  //定义16个8位的寄存器用于存放数据，FIFO管道//定义状态
parameter  S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;//用一段式状态机简单实现FIFO
always @(posedge clk or negedge rst_n) beginif(!rst_n) begincnt <= 0;wr_ptr <= 0;rd_ptr <= 0;dataout <= 0;endelse begincase ({rd,wr})S0 : begin   //空闲cnt <= cnt;wr_ptr <= wr_ptr;rd_ptr <= rd_ptr;dataout <= 0;endS1 : begin   //写FIOFif(!full) beginfifo_mem[wr_ptr] <= datain;wr_ptr <= wr_ptr + 1'b1;rd_ptr <= rd_ptr;cnt <= cnt + 1'b1;dataout <= 0;endend S2 : begin   //读FIFOif(!empt) begindataout <= fifo_mem[rd_ptr];rd_ptr <= rd_ptr + 1'b1;wr_ptr <= wr_ptr;cnt <= cnt - 1'b1;end end S3 : begin  //同时读写FIFOif(!full) beginfifo_mem[wr_ptr] <= datain;wr_ptr <= wr_ptr + 1'b1;end if(!empt) begindataout <= fifo_mem[rd_ptr];rd_ptr <= rd_ptr + 1'b1;end end default : ;endcaseend
end //满空标志信号产生
assign full = (cnt == 4'd15);
assign empt = (cnt == 4'd0 );endmodule

`timescale 1ns/1ns
module fifo_sync_tb();reg   clk;
reg     rst_n;
reg [7:0] datain;
reg     wr, rd;wire [7:0]   dataout;
wire    empt;
wire    full;initial begin
clk = 1'b1;
rst_n = 1'b0;
datain = 0;
wr = 1'b0;
rd = 1'b0;
#50
rst_n = 1'b1;
#40
wr = 1'b1;
#20
rd = 1'b1;
#20
rd = 1'b0;
#170
wr = 1'b0;
#200
rd = 1'b1;
#40
rd = 1'b0;
#500
$stop;
end always #5 clk = ~clk;always @(posedge clk) begindatain <= datain + 1'b1;
end fifo_sync fifo(.clk     (clk        ),.rst_n        (rst_n      ),.datain       (datain     ),  //输入数据.wr           (wr         ),  //写请求.rd            (rd         ),  //读请求.dataout   (dataout    ),  //输出数据.empt     (empt       ),  //空标志.full      (full       )   // 满标志
);endmodule