ad7606驱动及仿真

`timescale 1ns / 1ns
//
// Module Name:    ad7606
//
module ad7606(input                clk,                  //50mhzinput               rst_n,input [15:0]        ad_data,            //ad7606 采样数据input               ad_busy,            //ad7606 忙标志位input                first_data,         //ad7606 第一个数据标志位  output [2:0]        ad_os,              //ad7606 过采样倍率选择output reg          ad_cs,              //ad7606 AD csoutput reg          ad_rd,              //ad7606 AD data readoutput reg          ad_reset,           //ad7606 AD resetoutput reg          ad_convstab,         //ad7606 AD convert startoutput reg [15:0] ad_ch1,              //AD第1通道的数据output reg [15:0] ad_ch2,              //AD第2通道的数据output reg [15:0] ad_ch3,              //AD第3通道的数据output reg [15:0] ad_ch4,              //AD第4通道的数据output reg [15:0] ad_ch5,              //AD第5通道的数据output reg [15:0] ad_ch6,              //AD第6通道的数据output reg [15:0] ad_ch7,              //AD第7通道的数据output reg [15:0] ad_ch8,              //AD第8通道的数据  output reg [3:0]  state//output reg [3:0] cnt);reg [7:0] cnt = 0 ;
reg [15:0] cnt50us = 0;
reg [5:0] i;
//reg [3:0] state;parameter IDLE=4'd0;
parameter AD_CONV=4'd1;
parameter Wait_1=4'd2;
parameter Wait_busy=4'd3;
parameter READ_CH1=4'd4;
parameter READ_CH2=4'd5;
parameter READ_CH3=4'd6;
parameter READ_CH4=4'd7;
parameter READ_CH5=4'd8;
parameter READ_CH6=4'd9;
parameter READ_CH7=4'd10;
parameter READ_CH8=4'd11;
parameter READ_DONE=4'd12;
//parameter display=4'd13;assign ad_os=3'b000;  //无过采样//ad复位
always@(posedge clk)beginif(cnt<8'hff) begincnt<=cnt+1;ad_reset<=1'b1;endelsead_reset<=1'b0;  //计数器达到ff后停止，ad_reset恒为零     end//使用定时器来设置采样频率
always @(posedge clk or negedge rst_n) //每50us读取一次数据，ad的采样率为20Kbeginif(rst_n == 0)cnt50us <= 0;else begin if(cnt50us < 16'd2499)begincnt50us <= cnt50us + 1;endelsecnt50us <= 0;endendalways @(posedge clk) beginif (ad_reset==1'b1) begin   //初始化adstate<=IDLE; ad_ch1<=0;ad_ch2<=0;ad_ch3<=0;ad_ch4<=0;ad_ch5<=0;ad_ch6<=0;ad_ch7<=0;ad_ch8<=0;ad_cs<=1'b1;ad_rd<=1'b1; ad_convstab<=1'b1;   //8通道同步采样i<=0;end         else begincase(state)     //need time:(20+2+5+1+3*8+1)*20ns=1060ns, fmax=1/1060ns=1MHZIDLE: beginad_cs<=1'b1;ad_rd<=1'b1; ad_convstab<=1'b1; if(i==20) begin        //延时20个时钟后开始转换i<=0;           state<=AD_CONV;endelse i<=i+1'b1;endAD_CONV: begin       if(i==2) begin                        //等待2个lock，convstab的下降沿最少为25ns，故至少需要两个时钟i<=0;           state<=Wait_1;ad_convstab<=1'b1;                      endelse begini<=i+1'b1;ad_convstab<=1'b0;                     //启动AD转换endendWait_1: begin            if(i==5) begin                           //等待5个clock, 等待busy信号为高(tconv)i<=0;state<=Wait_busy;endelse i<=i+1'b1;end        Wait_busy: begin            if(ad_busy==1'b0) begin                    //等待busy为低电平  即转换之后读取模式i<=0;           state<=READ_CH1;endendREAD_CH1: begin ad_cs<=1'b0;                              //cs信号有效  直到读取8通道结束if(i==3) begin                            // 低电平持续3个时钟，完成通道1的读入ad_rd<=1'b1;i<=0;ad_ch1<=ad_data;                        //读CH1state<=READ_CH2;                endelse beginad_rd<=1'b0;   i<=i+1'b1;endendREAD_CH2: begin if(i==3) beginad_rd<=1'b1;i<=0;ad_ch2<=ad_data;                        //读CH2state<=READ_CH3;                endelse beginad_rd<=1'b0;   i<=i+1'b1;endendREAD_CH3: begin if(i==3) beginad_rd<=1'b1;i<=0;ad_ch3<=ad_data;                        //读CH3state<=READ_CH4;                endelse beginad_rd<=1'b0;   i<=i+1'b1;endendREAD_CH4: begin if(i==3) beginad_rd<=1'b1;i<=0;ad_ch4<=ad_data;                        //读CH4state<=READ_CH5;                endelse beginad_rd<=1'b0;   i<=i+1'b1;endendREAD_CH5: begin if(i==3) beginad_rd<=1'b1;i<=0;ad_ch5<=ad_data;                        //读CH5state<=READ_CH6;                endelse beginad_rd<=1'b0;   i<=i+1'b1;endendREAD_CH6: begin if(i==3) beginad_rd<=1'b1;i<=0;ad_ch6<=ad_data;                        //读CH6state<=READ_CH7;                endelse beginad_rd<=1'b0;   i<=i+1'b1;endendREAD_CH7: begin if(i==3) beginad_rd<=1'b1;i<=0;ad_ch7<=ad_data;                        //读CH7state<=READ_CH8;                endelse beginad_rd<=1'b0;   i<=i+1'b1;endendREAD_CH8: begin if(i==3) beginad_rd<=1'b1;i<=0;ad_ch8<=ad_data;                        //读CH8state<=READ_DONE;               endelse beginad_rd<=1'b0;   i<=i+1'b1;endendREAD_DONE:begin                                 //完成读，回到idle状态ad_rd<=1'b1;    ad_cs<=1'b1;if(cnt50us == 16'd2499)                      //不加此条件，则ad完成一次读取需1280ns，采样频率781.25K，但需注意ad每通道的追高采样只能为200Kstate<=IDLE;elsestate<=READ_DONE;end       default:  state<=IDLE;endcase   end   endendmodule

仿真测试程序如下：

`timescale 1 ns/ 1 ns
module ad7606_vlg_tst();
// constants
// general purpose registers// test vector input registers
reg ad_busy;
reg [15:0] ad_data;
reg clk;
reg first_data;
reg rst_n;
// wires
wire [15:0]  ad_ch1;
wire [15:0]  ad_ch2;
wire [15:0]  ad_ch3;
wire [15:0]  ad_ch4;
wire [15:0]  ad_ch5;
wire [15:0]  ad_ch6;
wire [15:0]  ad_ch7;
wire [15:0]  ad_ch8;
wire ad_convstab;
wire ad_cs;
wire [2:0]  ad_os;
wire ad_rd;
wire ad_reset;
wire [3:0] state;// assign statements (if any)
ad7606 i1 (
// port map - connection between master ports and signals/registers   .ad_busy(ad_busy),.ad_ch1(ad_ch1),.ad_ch2(ad_ch2),.ad_ch3(ad_ch3),.ad_ch4(ad_ch4),.ad_ch5(ad_ch5),.ad_ch6(ad_ch6),.ad_ch7(ad_ch7),.ad_ch8(ad_ch8),.ad_convstab(ad_convstab),.ad_cs(ad_cs),.ad_data(ad_data),.ad_os(ad_os),.ad_rd(ad_rd),.ad_reset(ad_reset),.clk(clk),.first_data(first_data),.rst_n(rst_n),.state(state)//.cnt(cnt)
);
initial                                                begin                                                  ad_busy = 0;first_data = 0;clk = 0;forever             //50MHz#10clk = ~clk;                                                                                                                                            $display("Running testbench");                       end
initialbeginrst_n = 1;#10;rst_n = 0;#20;rst_n = 1; endalways@(posedge clk)                        begin                                                  ad_data <= $random;      //使用随机数模拟采样信号        end  endmodule

仿真结果如下：

ad7606驱动及仿真相关推荐

Arduino与Proteus仿真实例-L298N驱动直流电机仿真
L298N驱动直流电机仿真 1.L298N介绍 L298N 是采用 15 引线多瓦和 PowerSO20 封装的集成单片电路. 它是一种高压.大电流双全桥驱动器,设计用于接受标准TTL逻辑电平和驱动电 ...
51单片机 IIC OLED屏幕驱动+Proteus仿真+实物验证示例程序
51单片机 IIC OLED屏幕驱动+Proteus仿真+实物验证示例程序 Proteus仿真效果注意点击运行仿真后,图像刷新出来比较慢. 示例主程序 #include "REG51.h& ...
Arduino与Proteus仿真实例-PCA9685驱动伺服电机仿真
PCA9685驱动伺服电机仿真 1.伺服电机介绍伺服电机是一种旋转执行器或线性执行器,可以精确控制角度或线性位置.速度和加速度. 它由一个合适的电机组成,该电机耦合到一个用于位置反馈的传感器. 它还 ...
Arduino与Proteus仿真实例-ULN2003驱动直流电机仿真
ULN2003驱动直流电机仿真 1.ULN2003介绍 ULN2003是最常用的电机驱动器 IC 之一,当我们需要使用数字逻辑电路(如 Op-map.定时器.门.Arduino.PIC.ARM 等)驱 ...
8051单片机Proteus仿真与开发实例-ULN2003A驱动步进电机仿真
ULN2003A驱动步进电机仿真 1.步进电机及ULN2003介绍步进电机是无刷直流电机,它能以固定的步距角旋转.步进电机一般采用200步完成360度旋转,即每一步旋转1.8度.可以通过适当的指令将 ...
Arduino与Proteus仿真实例-HG7881(L9110)驱动直流电机仿真
HG7881(L9110)驱动直流电机仿真 HG7881 (L9110) 双通道电机驱动器模块. HG7881 (L9110) 是一款紧凑型电机驱动芯片,支持 2.5-12V 电压范围,800mA 连 ...
FPGA Verilog AD7606驱动代码，包含SPI模式读取和并行模式读取两种
FPGA Verilog AD7606驱动代码,包含SPI模式读取和并行模式读取两种,代码注释详细编号:7428665912784264白衫如初oh
电驱动机电一体化仿真
背景电池替代发动机换来能量系统的空间自由,电驱动则突破了动力总成布局的边界约束,与此同时,整个动力底盘模块化加速,使得各子系统直接影响到整车性能乃至于用户体验. 一方面电驱动总成正在往集成化发展,以 ...
Arduino与Proteus仿真实例-L293D驱动直流电机仿真
L293D驱动直流电机仿真 L293D 是市场上最受欢迎的驱动程序之一. L293D成为用户首选的驱动器有几个原因,例如:价格便宜(与其他驱动器相比).合适的形状和尺寸.易于控制.无需保护电路和二极管 ...

ad7606驱动及仿真

ad7606驱动及仿真相关推荐

最新文章

热门文章