BIOS-CXL RcrbAccessLib 源码解析

文章目录

前言
1. RcrbAccessLib.c
- 1.1. ProgramMemBar0Register()
- 1.2. ClearMmioForCxlPort()
- 1.3. GetMemBar0()
2. Cxl20/Cxl20RcrbBaseLib.c
- 2.1. GetRcrbBar()
3. Spr/SprRcrbBaseLib.c
- 3.1. GetRcrbBar()
- 3.2. SetRcrbBar()
- 3.3. ClearRcrbBar()

前言

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1. RcrbAccessLib.c

1.1. ProgramMemBar0Register()

为 CXL 端口探测和设置 64bit MEMBAR0 寄存器。有一些寄存器只能写一次，不要探测这些寄存器。此外，probed size 在 MemBar0Size 中返回。


/**Routine to probe and program the 64-bit MEMBAR0 register for CXL port.Some reg can be writen ONCE. Don't probe for such reg, instead use thehardcoded value from MemBar0Size which provided by caller. Otherwise,the probed size is returned in MemBar0Size@param[in]      RcrbBaseAddr           RCRB base address@param[in]      BarRegOff              The offset of the Bar register@param[in]      MmioStartAddr          The start address of available MMIO resource@param[in]      Probe                  Probe the Membar0 size by writing FFFF?@param[out]     MemBar0Base            The pointer to the base address of MMIO resource allocated for MEMBAR0@param[in out]  MemBar0Size            The pointer to the size of MMIO resource requested by MEMBAR0@retval         EFI_SUCCESS            - Function return successfully.EFI_INVALID_PARAMETER  - Input parameter is invalid.
**/
EFI_STATUS
EFIAPI
ProgramMemBar0Register (IN      UINTN      RcrbBaseAddr,IN      UINT32     BarRegOff,IN      UINT32     MmioStartAddr,IN      BOOLEAN    Probe,OUT     UINT64     *MemBar0Base,IN OUT  UINT64     *MemBar0Size)
{UINT32     DataBuffer, Data32;UINT64     Data64;// 检查参数if (MemBar0Base == NULL || MemBar0Size == NULL) {DEBUG ((DEBUG_ERROR, "\nInvalid input parameters!!\n"));ASSERT (FALSE);return EFI_INVALID_PARAMETER;}//// Save the original low 32bit value of MEMBAR0// MEMBAR0 低32位的值DataBuffer = MmioRead32 (RcrbBaseAddr + BarRegOff);if (Probe == TRUE) {//// Probe the MEMBAR0 size// 向寄存器写全1，得到大小MmioWrite32 (RcrbBaseAddr + BarRegOff, 0xFFFFFFFF);  //Low 32 bitsMmioWrite32 (RcrbBaseAddr + BarRegOff + 4, 0xFFFFFFFF);  //High 32 bitsData32 = MmioRead32 (RcrbBaseAddr + BarRegOff + 4);  //Read back the high 32 bitsData64 = Data32;Data32 = MmioRead32 (RcrbBaseAddr + BarRegOff);  //Read back the low 32 bitsData32 &= 0xFFFFFFF0;  //Clearing the encoding information bits 0-3 for memoryData64 = LShiftU64 (Data64, 32) | Data32;// 写1可操作的位变为1，不可操作的仍然是0，所以最后一步要取反加1得出大小*MemBar0Size = ~Data64 + 1;}//// Adjust the MMIO base address to meet the alignment// 判断对齐*MemBar0Base = (MmioStartAddr + *MemBar0Size - 1) & (~(*MemBar0Size - 1));if ((UINT64) MmioStartAddr != *MemBar0Base) {DEBUG ((DEBUG_ERROR, "  Warning: Created a Memory Hole: 0x%x ~ 0x%x\n", MmioStartAddr, *MemBar0Base - 1));}DEBUG ((DEBUG_ERROR, "  MEMBAR0: Base = 0x%lx, Size = 0x%lx\n", *MemBar0Base, *MemBar0Size));//// Program the MEMBAR0 register// 设置 MEMBAR0 寄存器,写入原来的值Data32 = ((UINT32) (*MemBar0Base & 0xFFFFFFF0)) | (DataBuffer & 0xF);LogMmioWrite32 (RcrbBaseAddr + BarRegOff, Data32);Data32 = (UINT32) RShiftU64 (*MemBar0Base, 32);LogMmioWrite32 (RcrbBaseAddr + BarRegOff + 4, Data32);return EFI_SUCCESS;
}

1.2. ClearMmioForCxlPort()

常规清楚 64-bit MEMBAR0 寄存器

1.3. GetMemBar0()

使用 CXL RCRBBAR 寄存器得到 MEMBAR0 基地址


/**Get MEMBAR0 base address using the CXL RCRBBAR register.@param[in]  SocId     - Socket ID@param[in]  CtrId     - Controller ID@param[in]  BarRegOff - The offset of the Bar register@param[in]  Dp        - DP or UP, default is DP@retval               - The 64-bit RCRBBAR base address or 0 if failed.
**/
UINT64
EFIAPI
GetMemBar0 (IN  UINT8        SocId,IN  UINT8        CtrId,IN  UINT32       BarRegOff,IN  BOOLEAN      Dp)
{UINT32 RcrbBar;UINT64 MemBar0;UINT32 MemBar0High, MemBar0Low;// DP RCRBRcrbBar = (UINT32)GetRcrbBar (SocId, CtrId, TYPE_CXL_RCRB);if (RcrbBar == 0) {return 0;}if (Dp == FALSE) {// UP RCRB, Offset 4KRcrbBar += CXL_RCRB_BAR_SIZE_PER_PORT;}// 读 MemBar0 中的地址并返回MemBar0High = MmioRead32 (RcrbBar + BarRegOff + 4);MemBar0     = MemBar0High;MemBar0Low  = MmioRead32 (RcrbBar + BarRegOff);MemBar0Low &= 0xFFFFFFF0;  //Clearing the encoding information bits 0-3 for memoryMemBar0 = LShiftU64 (MemBar0, 32) | MemBar0Low;return MemBar0;
}

2. Cxl20/Cxl20RcrbBaseLib.c

2.1. GetRcrbBar()

从 CXL RCRBBAR 寄存器得到 RCRB 基地址


/**Get RCRB base address from the CXL RCRBBAR register.@param[in]  SocId           Socket ID@param[in]  CtrId           Controller ID@param[in]  CxlFlag         Unused; Keep it for compatibility@retval                     The 64-bit RCRBBAR base address or 0 if failed.
**/
UINT64
EFIAPI
GetRcrbBar (IN  UINT8                   SocId,IN  UINT8                   CtrId,IN  BOOLEAN                 CxlFlag)
{UINT64                      RcrbBarBase;CPU_CSR_ACCESS_VAR         *CpuCsrAccessVarPtr;// 使用系统函数获得CpuCsrAccessVarPtr = GetSysCpuCsrAccessVar();if (CpuCsrAccessVarPtr->Cxl1p1Rcrb[SocId][CtrId].Cxl1p1RcrbValid) {RcrbBarBase = CpuCsrAccessVarPtr->Cxl1p1Rcrb[SocId][CtrId].Cxl1p1RcrbBase;} else {RcrbBarBase = 0;}CXL_DEBUG_LOG ("\t%a (): RcrbBarBase = %x\n", __FUNCTION__, RcrbBarBase);return RcrbBarBase;
}

3. Spr/SprRcrbBaseLib.c

3.1. GetRcrbBar()

从 CXL RCRBBAR 寄存器得到 RCRB 基地址。接口平台相关，未找到相关资料


/**Get RCRBBAR base address from the CXL RCRBBAR register.@param[in]  SocId     - Socket ID@param[in]  CtrId     - Controller ID@param[in]  CxlFlag   - Indicate what type of the control, TRUE: Pcie G5 - CXL; FALSE: Pcie G4 - DMI@retval               - The 64-bit RCRBBAR base address or 0 if failed.
**/
UINT64
EFIAPI
GetRcrbBar (IN  UINT8        SocId,IN  UINT8        CtrId,IN  BOOLEAN      CxlFlag)
{UINT64                     RcrbBarBase;UINT32                     Data32;UINT32                     RcrbBarAddrLow, RcrbBarAddrHigh;CPU_CSR_ACCESS_VAR         *CpuCsrAccessVarPtr;if (CxlFlag) {CpuCsrAccessVarPtr = GetSysCpuCsrAccessVar();RcrbBarBase = CpuCsrAccessVarPtr->Cxl1p1Rcrb[SocId][CtrId].Cxl1p1RcrbBase;if (CpuCsrAccessVarPtr->Cxl1p1Rcrb[SocId][CtrId].Cxl1p1RcrbValid) {return RcrbBarBase;} else {DEBUG ((DEBUG_ERROR, "\nWARNING: CXL DP RCRBBAR is 0!!\n"));return 0;}} else {if ((((BIT0 << SocId) & GetPchPresentBitMap()) == 0) || (CtrId != 0)) {DEBUG ((DEBUG_ERROR, "\nInput parameter is invalid!\n"));ASSERT (FALSE);return 0;}RcrbBarAddrLow = RCRBBAR_N0_SB_PRVT_PCIE_G4_REG;RcrbBarAddrHigh = RCRBBAR_N1_SB_PRVT_PCIE_G4_REG;}Data32 = UsraCsrRead (SocId, CtrId, RcrbBarAddrHigh);RcrbBarBase = Data32;Data32 = UsraCsrRead (SocId, CtrId, RcrbBarAddrLow);RcrbBarBase = (LShiftU64 (RcrbBarBase, 32) | (Data32  & 0xFFFFFFFE));if (RcrbBarBase == 0) {DEBUG ((DEBUG_ERROR, "\nWARNING: CXL DP RCRBBAR is 0!!\n"));}return RcrbBarBase;
}

3.2. SetRcrbBar()

为 CXL or PCIe 端口设置 RcrbBar


/**Set RCRBBar for CXL or PCIe Port@param SocId                       Socket ID@param CtrId                       Controller ID@param CxlFlag                     Indicate what type of the control, TRUE: Pcie G5 - CXL; FALSE: Pcie G4 - DMI@param BarAddr                     RCRB Bar Address@retval                            - EFI_UNSUPPORTED: the function not implemented- EFI_SUCCESS: the function is excuted successfully
**/
EFI_STATUS
EFIAPI
SetRcrbBar (IN  UINT8                       SocId,IN  UINT8                       CtrId,IN  BOOLEAN                     CxlFlag,IN  UINT32                      BarAddr)
{RCRBBAR_N0_SB_PRVT_PCIE_G5_STRUCT     RcrbBarCxlDpN0;RCRBBAR_N0_SB_PRVT_PCIE_G4_STRUCT     RcrbBarDmiN0;CPU_CSR_ACCESS_VAR                    *CpuCsrAccessVarPtr;if (CxlFlag) {//// RCRB should be allocated below 4GB, so just program the N1 register to 0// RCRB 应该分配在 4G 以下UsraCsrWrite (SocId, CtrId, RCRBBAR_N1_SB_PRVT_PCIE_G5_REG, 0);//// Note:// By spec, the RcrbBar must be 8KB aligned.// - In this routine, the input BarAddr is likely to be the MmiolBase of the stack to which the CXL belongs, and//   it is directly programmed to RcrbBar register, which assumes the stack's MmiolBase is at least 8KB aligned.//RcrbBarCxlDpN0.Data = 0;RcrbBarCxlDpN0.Bits.baddr = BarAddr >> 13;RcrbBarCxlDpN0.Bits.en = 1;UsraCsrWrite (SocId, CtrId, RCRBBAR_N0_SB_PRVT_PCIE_G5_REG, RcrbBarCxlDpN0.Data);CpuCsrAccessVarPtr = GetSysCpuCsrAccessVar ();CpuCsrAccessVarPtr->Cxl1p1Rcrb[SocId][CtrId].Cxl1p1RcrbBase = BarAddr;CpuCsrAccessVarPtr->Cxl1p1Rcrb[SocId][CtrId].Cxl1p1RcrbValid = TRUE;} else {if (CtrId != 0) {DEBUG ((DEBUG_ERROR, "\nInput parameter is invalid!\n"));ASSERT (FALSE);return EFI_INVALID_PARAMETER;}UsraCsrWrite (SocId, CtrId, RCRBBAR_N1_SB_PRVT_PCIE_G4_REG, 0);RcrbBarDmiN0.Data = 0;RcrbBarDmiN0.Bits.baddr = BarAddr >> 13;RcrbBarDmiN0.Bits.en = 1;UsraCsrWrite (SocId, CtrId, RCRBBAR_N0_SB_PRVT_PCIE_G4_REG, RcrbBarDmiN0.Data);}DEBUG ((DEBUG_ERROR, "  %a (): RcrbBase = 0x%08X\n", __FUNCTION__, BarAddr));return EFI_SUCCESS;
}

3.3. ClearRcrbBar()

清除 RCRBBar


/**Clear RCRBBar for CXL or PCIe Port.@param[in]  SocId                      - Socket ID@param[in]  CtrId                      - Controller ID@param[in]  CxlFlag                    - Indicate what type of the control, TRUE: Pcie G5 - CXL; FALSE: Pcie G4 - DMI@retval     EFI_SUCCESS                - Function completed successfully@retval     EFI_INVALID_PARAMETER      - Fuction failed due to input parameter wrong
**/
EFI_STATUS
EFIAPI
ClearRcrbBar (IN  UINT8                       SocId,IN  UINT8                       CtrId,IN  BOOLEAN                     CxlFlag)
{if (CxlFlag) {UsraCsrWrite (SocId, CtrId, RCRBBAR_N1_SB_PRVT_PCIE_G5_REG, 0);UsraCsrWrite (SocId, CtrId, RCRBBAR_N0_SB_PRVT_PCIE_G5_REG, 0);} else {if ((SocId != GetSysSbspSocketIdNv ()) || (CtrId != 0)) {DEBUG ((DEBUG_ERROR, "\nInput parameter is invalid!\n"));ASSERT (FALSE);return EFI_INVALID_PARAMETER;}UsraCsrWrite (SocId, CtrId, RCRBBAR_N1_SB_PRVT_PCIE_G4_REG, 0);UsraCsrWrite (SocId, CtrId, RCRBBAR_N0_SB_PRVT_PCIE_G4_REG, 0);}return EFI_SUCCESS;
}

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BIOS-CXL RcrbAccessLib 源码解析

文章目录

前言

1. RcrbAccessLib.c

1.1. ProgramMemBar0Register()

1.2. ClearMmioForCxlPort()

1.3. GetMemBar0()

2. Cxl20/Cxl20RcrbBaseLib.c

2.1. GetRcrbBar()

3. Spr/SprRcrbBaseLib.c

3.1. GetRcrbBar()

3.2. SetRcrbBar()

3.3. ClearRcrbBar()

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