接上一篇，这一篇写得是内存初始化。本人对ddr初始化，不是特别懂。只是勉强翻译注释。如有错误，希望高手能不吝赐教。废话不多说，贴上这该死的代码。

/**  armboot - Memory Initialize Code for S5PV210/ARM-Cortex CPU-core**  Copyright (c) 2009  Samsung Electronics*** See file CREDITS for list of people who contributed to this* project.** This program is free software; you can redistribute it and/or* modify it under the terms of the GNU General Public License as* published by the Free Software Foundation; either version 2 of* the License, or (at your option) any later version.** This program is distributed in the hope that it will be useful,* but WITHOUT ANY WARRANTY; without even the implied warranty of* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the* GNU General Public License for more details.** You should have received a copy of the GNU General Public License* along with this program; if not, write to the Free Software* Foundation, Inc., 59 Temple Place, Suite 330, Boston,* MA 02111-1307 USA** Base codes by scsuh  (sc.suh)* Modified By JhoonKim (jhoon_kim@nate.com), aESOP Embedded Forum(http://www.aesop.or.kr)* 10.08.15 - To Supported for SEC K4T1G164QX DDR2 Memory for aESOP S5PV210*/#include <config.h>
#include <s5pc110.h>.globl mem_ctrl_asm_init    //全局变量
mem_ctrl_asm_init:#ifndef CONFIG_EVT1 //由于定义过，所以再次不用分析ldr     r0, =ASYNC_MSYS_DMC0_BASE   //0xF1E00000ldr     r1, =0x0str     r1, [r0, #0x0]/* This register is removed at EVT1 of C110. */ldr     r1, =0x0str     r1, [r0, #0xC]#endif#ifdef CONFIG_MCP_SINGLE/* DMC0 Drive Strength (Setting 2X) 设置内存访问信号的强度*//*DRAM Driver Strength 数值越大，则内存访问信号的强度也越大。内存对工作频率是比较敏感的，当工作频率高于内存的标称频率时， 将该选项的数值调高， 可以提高电脑在超频状态下的稳定性*/ldr r0, =ELFIN_GPIO_BASE    //0xE0200000ldr r1, =0x0000AAAAstr r1, [r0, #MP1_0DRV_SR_OFFSET]   //0xE020_03CCldr r1, =0x0000AAAAstr r1, [r0, #MP1_1DRV_SR_OFFSET]   //0xE020_03ECldr r1, =0x0000AAAAstr r1, [r0, #MP1_2DRV_SR_OFFSET]   //0xE020_040Cldr r1, =0x0000AAAAstr r1, [r0, #MP1_3DRV_SR_OFFSET]   //0xE020_042Cldr r1, =0x0000AAAAstr r1, [r0, #MP1_4DRV_SR_OFFSET]   //0xE020_044Cldr r1, =0x0000AAAAstr r1, [r0, #MP1_5DRV_SR_OFFSET]   //0xE020_046Cldr r1, =0x0000AAAAstr r1, [r0, #MP1_6DRV_SR_OFFSET]   //0xE020_048Cldr r1, =0x0000AAAAstr r1, [r0, #MP1_7DRV_SR_OFFSET]   //0xE020_04ACldr r1, =0x00002AAAstr r1, [r0, #MP1_8DRV_SR_OFFSET]   //0xE020_04CC/* DMC1 Drive Strength (Setting 2X) */ldr r0, =ELFIN_GPIO_BASE    //0xE0200000 形同上面，就不细细的写了ldr r1, =0x0000AAAAstr r1, [r0, #MP2_0DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP2_1DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP2_2DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP2_3DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP2_4DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP2_5DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP2_6DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP2_7DRV_SR_OFFSET]ldr r1, =0x00002AAAstr r1, [r0, #MP2_8DRV_SR_OFFSET]/* DMC0 initialization at single Type 初始化PHY DLL *//* 凡是使用 DDR 类型的 DRAM，都需要使用 DLL(Delay Locked Loop 延时锁定回路提供一个数据滤波信号)技术，当数据有效时，存储控制器可使用这个数据滤波信号来精确定位数据。*/ldr r0, =APB_DMC_0_BASE //0xF000_0000ldr r1, =0x00101000             @PhyControl0 DLL parameter setting, manual 0x00101000/*bit[15:8] DLL Lock Start Point Initial DLL lock start point. This is the number of delay cells and is the start point where "DLL" start tracing to lock. CalculatesInitial delay time by multiplying the unit delay of delay cell and this value. This value should be 0x10bit [23:16] DLL Delay Increment Increase the amount of start point 这个值应该设置为0x10*/str r1, [r0, #DMC_PHYCONTROL0]  //PHY Control0 Register(0xF000_0018)ldr r1, =0x00000086             @PhyControl1 DLL parameter setting, LPDDR/LPDDR2 Casestr r1, [r0, #DMC_PHYCONTROL1]  //0xF000_001C PHY Control1 Registerldr r1, =0x00101002             @PhyControl0 DLL onstr r1, [r0, #DMC_PHYCONTROL0]  //0xF000_0018ldr r1, =0x00101003             @PhyControl0 DLL startstr r1, [r0, #DMC_PHYCONTROL0]  //0xF000_0018find_lock_val:ldr r1, [r0, #DMC_PHYSTATUS]        @Load Phystatus register value 0xF000_0040and r2, r1, #0x7cmp r2, #0x7                @Loop until DLL is lockedbne find_lock_valand r1, #0x3fc0mov r2, r1, LSL #18orr r2, r2, #0x100000orr r2 ,r2, #0x1000orr r1, r2, #0x3                @Force Value lockingstr r1, [r0, #DMC_PHYCONTROL0]  //0xF000_0018#if 0   /* Memory margin test 10.01.05 */orr r1, r2, #0x1                @DLL offstr r1, [r0, #DMC_PHYCONTROL0]
#endif/* setting DDR2 */ldr r1, =0x0FFF2010             @ConControl auto refresh offstr r1, [r0, #DMC_CONCONTROL]ldr r1, =DMC0_MEMCONTROL            @MemControl BL=4, 1 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down offstr r1, [r0, #DMC_MEMCONTROL]ldr r1, =DMC0_MEMCONFIG_0           @MemConfig0 256MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixedstr r1, [r0, #DMC_MEMCONFIG0]ldr r1, =DMC0_MEMCONFIG_1           @MemConfig1str r1, [r0, #DMC_MEMCONFIG1]ldr r1, =0xFF000000             @PrechConfigstr r1, [r0, #DMC_PRECHCONFIG]ldr r1, =DMC0_TIMINGA_REF           @TimingAref 7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4E)str r1, [r0, #DMC_TIMINGAREF]ldr r1, =DMC0_TIMING_ROW            @TimingRow  for @200MHzstr r1, [r0, #DMC_TIMINGROW]ldr r1, =DMC0_TIMING_DATA           @TimingData CL=4str r1, [r0, #DMC_TIMINGDATA]ldr r1, =DMC0_TIMING_PWR            @TimingPowerstr r1, [r0, #DMC_TIMINGPOWER]ldr r1, =0x07000000             @DirectCmd  chip0 Deselectstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x01000000             @DirectCmd  chip0 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00020000             @DirectCmd  chip0 EMRS2str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00030000             @DirectCmd  chip0 EMRS3str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00010400             @DirectCmd  chip0 EMRS1 (MEM DLL on, DQS# disable)str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00000542             @DirectCmd  chip0 MRS (MEM DLL reset) CL=4, BL=4str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x01000000             @DirectCmd  chip0 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x05000000             @DirectCmd  chip0 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x05000000             @DirectCmd  chip0 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00000442             @DirectCmd  chip0 MRS (MEM DLL unreset)str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00010780             @DirectCmd  chip0 EMRS1 (OCD default)str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00010400             @DirectCmd  chip0 EMRS1 (OCD exit)str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x07100000             @DirectCmd  chip1 Deselectstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x01100000             @DirectCmd  chip1 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00120000             @DirectCmd  chip1 EMRS2str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00130000             @DirectCmd  chip1 EMRS3str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00110400             @DirectCmd  chip1 EMRS1 (MEM DLL on, DQS# disable)str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00100542             @DirectCmd  chip1 MRS (MEM DLL reset) CL=4, BL=4str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x01100000             @DirectCmd  chip1 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x05100000             @DirectCmd  chip1 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x05100000             @DirectCmd  chip1 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00100442             @DirectCmd  chip1 MRS (MEM DLL unreset)str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00110780             @DirectCmd  chip1 EMRS1 (OCD default)str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00110400             @DirectCmd  chip1 EMRS1 (OCD exit)str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x0FF02030             @ConControl auto refresh onstr r1, [r0, #DMC_CONCONTROL]ldr r1, =0xFFFF00FF             @PwrdnConfigstr r1, [r0, #DMC_PWRDNCONFIG]ldr r1, =0x00202400             @MemControl BL=4, 1 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down offstr r1, [r0, #DMC_MEMCONTROL]/* DMC1 initialization */ldr r0, =APB_DMC_1_BASEldr r1, =0x00101000             @Phycontrol0 DLL parameter settingstr r1, [r0, #DMC_PHYCONTROL0]ldr r1, =0x00000086             @Phycontrol1 DLL parameter settingstr r1, [r0, #DMC_PHYCONTROL1]ldr r1, =0x00101002             @PhyControl0 DLL onstr r1, [r0, #DMC_PHYCONTROL0]ldr r1, =0x00101003             @PhyControl0 DLL startstr r1, [r0, #DMC_PHYCONTROL0]
find_lock_val1:ldr r1, [r0, #DMC_PHYSTATUS]        @Load Phystatus register valueand r2, r1, #0x7cmp r2, #0x7                @Loop until DLL is lockedbne find_lock_val1and r1, #0x3fc0mov r2, r1, LSL #18orr r2, r2, #0x100000orr r2, r2, #0x1000orr r1, r2, #0x3                @Force Value lockingstr r1, [r0, #DMC_PHYCONTROL0]#if 0   /* Memory margin test 10.01.05 */orr r1, r2, #0x1                @DLL offstr r1, [r0, #DMC_PHYCONTROL0]
#endif/* settinf fot DDR2 */ldr r0, =APB_DMC_1_BASEldr r1, =0x0FFF2010             @auto refresh offstr r1, [r0, #DMC_CONCONTROL]ldr r1, =DMC1_MEMCONTROL            @MemControl BL=4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down offstr r1, [r0, #DMC_MEMCONTROL]ldr r1, =DMC1_MEMCONFIG_0           @MemConfig0 512MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixedstr r1, [r0, #DMC_MEMCONFIG0]ldr r1, =DMC1_MEMCONFIG_1           @MemConfig1str r1, [r0, #DMC_MEMCONFIG1]ldr r1, =0xFF000000str r1, [r0, #DMC_PRECHCONFIG]ldr r1, =DMC1_TIMINGA_REF           @TimingAref 7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4str r1, [r0, #DMC_TIMINGAREF]ldr r1, =DMC1_TIMING_ROW            @TimingRow  for @200MHzstr r1, [r0, #DMC_TIMINGROW]ldr r1, =DMC1_TIMING_DATA           @TimingData CL=3str r1, [r0, #DMC_TIMINGDATA]ldr r1, =DMC1_TIMING_PWR            @TimingPowerstr r1, [r0, #DMC_TIMINGPOWER]ldr r1, =0x07000000             @DirectCmd  chip0 Deselectstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x01000000             @DirectCmd  chip0 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00020000             @DirectCmd  chip0 EMRS2str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00030000             @DirectCmd  chip0 EMRS3str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00010400             @DirectCmd  chip0 EMRS1 (MEM DLL on, DQS# disable)str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00000542             @DirectCmd  chip0 MRS (MEM DLL reset) CL=4, BL=4str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x01000000             @DirectCmd  chip0 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x05000000             @DirectCmd  chip0 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x05000000             @DirectCmd  chip0 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00000442             @DirectCmd  chip0 MRS (MEM DLL unreset)str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00010780             @DirectCmd  chip0 EMRS1 (OCD default)str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00010400             @DirectCmd  chip0 EMRS1 (OCD exit)str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x07100000             @DirectCmd  chip1 Deselectstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x01100000             @DirectCmd  chip1 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00120000             @DirectCmd  chip1 EMRS2str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00130000             @DirectCmd  chip1 EMRS3str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00110440             @DirectCmd  chip1 EMRS1 (MEM DLL on, DQS# disable)str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00100542             @DirectCmd  chip1 MRS (MEM DLL reset) CL=4, BL=4str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x01100000             @DirectCmd  chip1 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x05100000             @DirectCmd  chip1 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x05100000             @DirectCmd  chip1 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00100442             @DirectCmd  chip1 MRS (MEM DLL unreset)str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00110780             @DirectCmd  chip1 EMRS1 (OCD default)str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00110400             @DirectCmd  chip1 EMRS1 (OCD exit)str r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x0FF02030             @ConControl auto refresh onstr r1, [r0, #DMC_CONCONTROL]ldr r1, =0xFFFF00FF             @PwrdnConfigstr r1, [r0, #DMC_PWRDNCONFIG]ldr r1, =DMC1_MEMCONTROL            @MemControl BL=4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down offstr r1, [r0, #DMC_MEMCONTROL]#else   /* CONFIG_MCP_SINGLE *//* DMC0 initialization */ldr r0, =APB_DMC_0_BASEldr r1, =0x00101000             @Phycontrol0 DLL parameter settingstr r1, [r0, #DMC_PHYCONTROL0]ldr r1, =0x00000084             @Phycontrol1 DLL parameter settingstr r1, [r0, #DMC_PHYCONTROL1]ldr r1, =0x00101002             @Phycontrol2 DLL parameter settingstr r1, [r0, #DMC_PHYCONTROL0]ldr r1, =0x00101003             @Dll onstr r1, [r0, #DMC_PHYCONTROL0]find_lock_val:ldr r1, [r0, #DMC_PHYSTATUS]        @Load Phystatus register valueand     r2, r1, #0x7cmp r2, #0x7                @Loop until DLL is lockedbne find_lock_valand r1, #0x3fc0mov r2, r1, LSL #18orr r2, r2, #0x100000orr r2, r2, #0x1000orr r1, r2, #0x3                @Force Value lockingstr r1, [r0, #DMC_PHYCONTROL0]
#if 1 /* DRAM margin test 10.01.06 */orr r1, r2, #0x1                @DLL offstr r1, [r0, #DMC_PHYCONTROL0]
#endifldr r1, =0x0fff1010             @auto refresh offstr r1, [r0, #DMC_CONCONTROL]ldr r1, =0x00212100str r1, [r0, #DMC_MEMCONTROL]ldr r1, =DMC0_MEMCONFIG_0str r1, [r0, #DMC_MEMCONFIG0]ldr r1, =DMC0_MEMCONFIG_1str r1, [r0, #DMC_MEMCONFIG1]ldr r1, =0xff000000str r1, [r0, #DMC_PRECHCONFIG]ldr r1, =DMC0_TIMINGA_REFstr r1, [r0, #DMC_TIMINGAREF]ldr r1, =DMC0_TIMING_ROW            @TimingRow  @133MHzstr r1, [r0, #DMC_TIMINGROW]ldr r1, =DMC0_TIMING_DATAstr r1, [r0, #DMC_TIMINGDATA]ldr r1, =DMC0_TIMING_PWR            @Timing Powerstr r1, [r0, #DMC_TIMINGPOWER]ldr r1, =0x07000000             @chip0 Deselectstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x01000000             @chip0 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x05000000             @chip0 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x05000000             @chip0 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00000032             @chip0 MRSstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x07100000             @chip1 Deselectstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x01100000             @chip1 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x05100000             @chip1 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x05100000             @chip1 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00100032             @chip1 MRSstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x0FFF20B0         @ConControl auto refresh onstr r1, [r0, #DMC_CONCONTROL]ldr r1, =0xFFFF00FF             @PwrdnConfigstr r1, [r0, #DMC_PWRDNCONFIG]ldr r1, =0x00212113             @MemControlstr r1, [r0, #DMC_MEMCONTROL]/* DMC1 initialization */ldr r0, =APB_DMC_1_BASEldr r1, =0x00101000             @Phycontrol0 DLL parameter settingstr r1, [r0, #DMC_PHYCONTROL0]ldr r1, =0x00000084             @Phycontrol1 DLL parameter settingstr r1, [r0, #DMC_PHYCONTROL1]ldr r1, =0x00101002             @Phycontrol2 DLL parameter settingstr r1, [r0, #DMC_PHYCONTROL0]ldr r1, =0x00101003             @Dll onstr r1, [r0, #DMC_PHYCONTROL0]find_lock_val1:ldr r1, [r0, #DMC_PHYSTATUS]        @Load Phystatus register valueand     r2, r1, #0x7cmp r2, #0x7                @Loop until DLL is lockedbne find_lock_val1and r1, #0x3fc0mov r2, r1, LSL #18orr r2, r2, #0x100000orr r2, r2, #0x1000orr r1, r2, #0x3                @Force Value lockingstr r1, [r0, #DMC_PHYCONTROL0]#if 1   /* Memory margin test 10.01.05 */orr r1, r2, #0x1                @DLL offstr r1, [r0, #DMC_PHYCONTROL0]
#endifldr r0, =APB_DMC_1_BASEldr r1, =0x0FFF1010             @auto refresh offstr r1, [r0, #DMC_CONCONTROL]ldr r1, =0x00212100str r1, [r0, #DMC_MEMCONTROL]ldr r1, =DMC1_MEMCONFIG_0str r1, [r0, #DMC_MEMCONFIG0]ldr r1, =DMC1_MEMCONFIG_1str r1, [r0, #DMC_MEMCONFIG1]ldr r1, =0xff000000str r1, [r0, #DMC_PRECHCONFIG]ldr r1, =DMC1_TIMINGA_REFstr r1, [r0, #DMC_TIMINGAREF]ldr r1, =DMC1_TIMING_ROW            @TimingRow  @133MHzstr r1, [r0, #DMC_TIMINGROW]ldr r1, =DMC1_TIMING_DATAstr r1, [r0, #DMC_TIMINGDATA]ldr r1, =DMC1_TIMING_PWR            @Timing Powerstr r1, [r0, #DMC_TIMINGPOWER]ldr r1, =0x07000000             @chip0 Deselectstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x01000000             @chip0 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x05000000             @chip0 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x05000000             @chip0 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00000032             @chip0 MRSstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00020020             @chip0 EMRSstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x07100000             @chip1 Deselectstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x01100000             @chip1 PALLstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x05100000             @chip1 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x05100000             @chip1 REFAstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00100032             @chip1 MRSstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x00120020             @chip0 EMRSstr r1, [r0, #DMC_DIRECTCMD]ldr r1, =0x0FFF10B0             @ConControl auto refresh onstr r1, [r0, #DMC_CONCONTROL]ldr r1, =0xFFFF00FF             @PwrdnConfigstr r1, [r0, #DMC_PWRDNCONFIG]ldr r1, =0x00212113             @MemControlstr r1, [r0, #DMC_MEMCONTROL]#endif  /* CONFIG_MCP_AC / CONFIG_MCP_H / CONFIG_MCP_B / CONFIG_MCP_D */mov pc, lr/* Below code is for ARM926EJS and ARM1026EJS */.globl cleanDCache
cleanDCache:mrc p15, 0, pc, c7, c10, 3  /* test/clean D-Cache */bne cleanDCachemov pc, lr.globl cleanFlushDCache
cleanFlushDCache:mrc p15, 0, pc, c7, c14, 3  /* test/cleanflush D-Cache */bne cleanFlushDCachemov pc, lr.globl cleanFlushCache
cleanFlushCache:mrc p15, 0, pc, c7, c14, 3  /* test/cleanflush D-Cache */bne cleanFlushCachemcr p15, 0, r0, c7, c5, 0   /* flush I-Cache */mov pc, lr.ltorg/**     v7_flush_dcache_all()**     Flush the whole D-cache.**     Corrupted registers: r0-r5, r7, r9-r11**     - mm    - mm_struct describing address space*/.align 5
.global v7_flush_dcache_all
v7_flush_dcache_all:ldr     r0, =0xffffffffmrc     p15, 1, r0, c0, c0, 1           @ Read CLIDRands    r3, r0, #0x7000000mov     r3, r3, LSR #23                 @ Cache level value (naturally aligned)beq     Finishedmov     r10, #0
Loop1:add     r2, r10, r10, LSR #1            @ Work out 3xcachelevelmov     r1, r0, LSR r2                  @ bottom 3 bits are the Ctype for this leveland     r1, r1, #7                      @ get those 3 bits alonecmp     r1, #2blt     Skip                            @ no cache or only instruction cache at this levelmcr     p15, 2, r10, c0, c0, 0          @ write the Cache Size selection registermov     r1, #0mcr     p15, 0, r1, c7, c5, 4           @ PrefetchFlush to sync the change to the CacheSizeID regmrc     p15, 1, r1, c0, c0, 0           @ reads current Cache Size ID registerand     r2, r1, #0x7                    @ extract the line length fieldadd     r2, r2, #4                      @ add 4 for the line length offset (log2 16 bytes)ldr     r4, =0x3FFands    r4, r4, r1, LSR #3              @ R4 is the max number on the way size (right aligned)clz     r5, r4                          @ R5 is the bit position of the way size incrementldr     r7, =0x00007FFFands    r7, r7, r1, LSR #13             @ R7 is the max number of the index size (right aligned)
Loop2:mov     r9, r4                          @ R9 working copy of the max way size (right aligned)
Loop3:orr     r11, r10, r9, LSL r5            @ factor in the way number and cache number into R11orr     r11, r11, r7, LSL r2            @ factor in the index numbermcr     p15, 0, r11, c7, c6, 2          @ invalidate by set/waysubs    r9, r9, #1                      @ decrement the way numberbge     Loop3subs    r7, r7, #1                      @ decrement the indexbge     Loop2
Skip:add     r10, r10, #2                    @ increment the cache numbercmp     r3, r10bgt     Loop1
Finished:mov     pc, lr.align  5
.global disable_l2cache
disable_l2cache:mrc     p15, 0, r0, c1, c0, 1bic     r0, r0, #(1<<1)mcr     p15, 0, r0, c1, c0, 1mov     pc, lr.align  5
.global enable_l2cache
enable_l2cache:mrc     p15, 0, r0, c1, c0, 1orr     r0, r0, #(1<<1)mcr     p15, 0, r0, c1, c0, 1mov     pc, lr.align  5
.global set_l2cache_auxctrl
set_l2cache_auxctrl:mov     r0, #0x0mcr     p15, 1, r0, c9, c0, 2mov     pc, lr.align  5
.global set_l2cache_auxctrl_cycle
set_l2cache_auxctrl_cycle:mrc     p15, 1, r0, c9, c0, 2bic     r0, r0, #(0x1<<29)bic     r0, r0, #(0x1<<21)bic     r0, r0, #(0x7<<6)bic     r0, r0, #(0x7<<0)mcr     p15, 1, r0, c9, c0, 2mov     pc,lr.align 5
CoInvalidateDCacheIndex:;/* r0 = index */mcr     p15, 0, r0, c7, c6, 2mov     pc,lr

如果你觉得写得还行，转载时请保留作者信息。作者：捷宇 邮箱：jayyuz@163.com 博客:http://blog.csdn.net/jayyuz

s5pv210 u-boot的那些事儿之---mem_setup.S的分析相关推荐

  1. s5pv210 SD boot (1)

    奇怪的是,为什么折腾了2天多了,SD仍然不能升级. 在XP下:SD Flasher可以运行,但貌似并没有写进去. 在Win7虚拟机下:Relayout的时候,提示ERROR ReadOnly Medi ...

  2. s5pv210 u-boot的那些事儿之---lowleve_init.S的分析

    最近一直在学习研究u-boot,这是我对s5pv210的u-boot的一些学习的一些列的文章中的一部分.这是我的注释代码,希望能帮到正在学习的你们. /** Memory Setup stuff - ...

  3. Spring Boot下Druid连接池的使用配置分析

    引言: 在Spring Boot下默认提供了若干种可用的连接池,Druid来自于阿里系的一个开源连接池,在连接池之外,还提供了非常优秀的监控功能,这里讲解如何与Spring Boot实现集成. 1.  ...

  4. spring boot实战(第九篇)Application创建源码分析

    前言 通过前面的文章了解到在spring boot的启动时,利用的是编写的Application类,使用了注解@SpringBootApplication,本篇将阐述该Bean的加载过程. [html ...

  5. Spring Boot基础学习笔记02：Spring Boot项目单元测试、热部署与原理分析

    文章目录 零.学习目标 1.掌握Spring Boot单元测试实现 2.掌握Spring Boot热部署实现 3.熟悉Spring Boot基本原理 一.Spring Boot单元测试 (一)Spri ...

  6. FreeNOS-kernel目录下boot.S、链接脚本kernel.ld文件分析（四）

    上节提到过引导程序在将控制权交给内核时,相关寄存器状态已确定,并且程序入口地址为boot.S文件中的_start,下个面就来看看boot.S文件. kernel目录下文件如下: 其中Sconscrip ...

  7. 《深入实践Spring Boot》阅读笔记之三：核心技术源代码分析

    为什么80%的码农都做不了架构师?>>>    刚关注的朋友,可以回顾前两篇文章: 基础应用开发 分布式应用开发 上篇文章总结了<深入实践Spring Boot>的第二部 ...

  8. 滑动窗口限流 java_Spring Boot 的接口限流算法优缺点深度分析

    点击上方蓝色字体,选择"标星公众号" 优质文章,第一时间送达 上一篇:这300G的Java资料是我师傅当年给我的,免费分享给大家(已修复) 下一篇:昨天分享资料不小心把百度网盘深处 ...

  9. Spring Boot 的接口限流算法优缺点深度分析

最新文章

  1. HTML学习笔记——选择器
  2. c++ 原子操作 赋值_原子操作原理
  3. Leetcode 118 杨辉三角
  4. 【论文阅读】Fully Convolutional Networks for Semantic Segmentation
  5. ffmpeg文档1:制作屏幕录像
  6. python毕业设计作品基于django框架 二手物品交易系统毕设成品（2）网站功能
  7. Ubuntu64位安装Adobe Reader 9.5.5
  8. phpwind9.0 read.php 修改,phpwind 9.0后台执行任意php代码
  9. kotlin-stdlib 与 kotlin-stdlib-jdk7
  10. 正高职称 程序员_软考通过之后，如何评职称呢？
  11. SCAU程序设计在线实训平台_实验_高级语言程序设计_教材习题_第七章
  12. HIVE获取时间函数, regexp_extract正则提取用法
  13. linux如何访问共享目录权限设置密码,文件夹如何设置密码_在共享文件夹上怎么设置密码访问 - 驱动管家...
  14. python 制作抽奖_python制作抽奖程序代码详解
  15. linux新建磁盘分区
  16. zabbix 监控域名注册到期时间
  17. 【C语言】关于“LNK1168”的错误
  18. Linux安装rz命令和sz命令方法教程
  19. [CDH官方文档]--CDH最新官方文档(最全)
  20. java程序设计项目案例化教程题库及答案

热门文章

  1. Tini 源码分析(2)
  2. 迅为iTOP-2K1000开发板龙芯中科国产64位Loognix系统工业核心主板
  3. 基于嵌入式Linux的测温系统,基于嵌入式Linux的图像监控系统
  4. 程序员成神之路，一年挖坑，五年扛旗，十年成神
  5. vs读取mysql数据库文件_VS 读写sql server 完整步骤
  6. html4角星,四角星是什么意思 四个角的星星我想你了是什么套路
  7. #Table纵向滚动时表头固定 [ position:sticky ]
  8. 简单返回顶部代码及注释说明（转）
  9. c语言程序设计学生管理系统结构图,c语言程序设计学生管理系统.doc
  10. REGEXP_REPLACE的使用方法