【TX2】TX2开发板系统默认串口有ttyS0（调试口）、ttyTHS1、ttyTHS2、ttyTHS3，通过修改设备树文件，可以新增三个串口
2024-04-15 11:51:59
1、简述
TX2开发板系统默认串口有ttyS0（调试口）、ttyTHS1、ttyTHS2、ttyTHS3，通过修改设备树文件，可以新增三个串口。
2、设备树
设备树中关于串口部分的描述
2.1 基础配置
注意：在这里状态都配置成禁止（status = “disabled”;）
在设备树描述文件tegra186-quill-common.dtsi中，根据需要配置成使能（status = “okay”;）
sources/hardware/nvidia/soc/t18x/kernel-dts/tegra186-soc/tegra186-soc-uart.dtsi
/*tegra186-soc-uart.dtsi: Tegra186 soc dtsi file for UART instances*/
/ {uarta: serial@3100000 {compatible = "nvidia,tegra20-uart";#stream-id-cells = <1>;reg = <0x0 0x03100000 0x0 0x40>;reg-shift = <2>;interrupts = <0 TEGRA186_IRQ_UARTA 0x04>;nvidia,memory-clients = <14>;dmas = <&gpcdma 8>, <&gpcdma 8>;dma-names = "rx", "tx";clocks = <&tegra_car TEGRA186_CLK_UARTA>,<&tegra_car TEGRA186_CLK_PLLP_OUT0>;clock-names = "serial", "parent";resets = <&tegra_car TEGRA186_RESET_UARTA>;reset-names = "serial";status = "disabled";nvidia,adjust-baud-rates = <115200 115200 100>;};uartb: serial@3110000 {compatible = "nvidia,tegra186-hsuart";#stream-id-cells = <1>;reg = <0x0 0x03110000 0x0 0x40>;reg-shift = <2>;interrupts = <0 TEGRA186_IRQ_UARTB 0x04>;nvidia,memory-clients = <14>;dmas = <&gpcdma 9>, <&gpcdma 9>;dma-names = "rx", "tx";clocks = <&tegra_car TEGRA186_CLK_UARTB>,<&tegra_car TEGRA186_CLK_PLLP_OUT0>;clock-names = "serial", "parent";resets = <&tegra_car TEGRA186_RESET_UARTB>;reset-names = "serial";status = "disabled";nvidia,adjust-baud-rates = <115200 115200 100>;};uartc: serial@c280000 {compatible = "nvidia,tegra186-hsuart";#stream-id-cells = <1>;reg = <0x0 0xc280000 0x0 0x40>;reg-shift = <2>;interrupts = <0 TEGRA186_IRQ_UARTC 0x04>;nvidia,memory-clients = <14>;dmas = <&gpcdma 3>, <&gpcdma 3>;dma-names = "rx", "tx";clocks = <&tegra_car TEGRA186_CLK_UARTC>,<&tegra_car TEGRA186_CLK_PLLP_OUT0>;clock-names = "serial", "parent";resets = <&tegra_car TEGRA186_RESET_UARTC>;reset-names = "serial";status = "disabled";nvidia,adjust-baud-rates = <115200 115200 100>;};uartd: serial@3130000 {compatible = "nvidia,tegra186-hsuart";#stream-id-cells = <1>;reg = <0x0 0x03130000 0x0 0x40>;reg-shift = <2>;interrupts = <0 TEGRA186_IRQ_UARTD 0x04>;nvidia,memory-clients = <14>;dmas = <&gpcdma 19>, <&gpcdma 19>;dma-names = "rx", "tx";clocks = <&tegra_car TEGRA186_CLK_UARTD>,<&tegra_car TEGRA186_CLK_PLLP_OUT0>;clock-names = "serial", "parent";resets = <&tegra_car TEGRA186_RESET_UARTD>;reset-names = "serial";status = "disabled";nvidia,adjust-baud-rates = <115200 115200 100>;};uarte: serial@3140000 {compatible = "nvidia,tegra186-hsuart";#stream-id-cells = <1>;reg = <0x0 0x03140000 0x0 0x40>;reg-shift = <2>;interrupts = <0 TEGRA186_IRQ_UARTE 0x04>;nvidia,memory-clients = <14>;dmas = <&gpcdma 20>, <&gpcdma 20>;dma-names = "rx", "tx";clocks = <&tegra_car TEGRA186_CLK_UARTE>,<&tegra_car TEGRA186_CLK_PLLP_OUT0>;clock-names = "serial", "parent";resets = <&tegra_car TEGRA186_RESET_UARTE>;reset-names = "serial";status = "disabled";nvidia,adjust-baud-rates = <115200 115200 100>;};uartf: serial@3150000 {compatible = "nvidia,tegra186-hsuart";#stream-id-cells = <1>;reg = <0x0 0x03150000 0x0 0x40>;reg-shift = <2>;interrupts = <0 TEGRA186_IRQ_UARTF 0x04>;nvidia,memory-clients = <14>;dmas = <&gpcdma 12>, <&gpcdma 12>;dma-names = "rx", "tx";clocks = <&tegra_car TEGRA186_CLK_UARTF>,<&tegra_car TEGRA186_CLK_PLLP_OUT0>;clock-names = "serial", "parent";resets = <&tegra_car TEGRA186_RESET_UARTF>;reset-names = "serial";status = "disabled";nvidia,adjust-baud-rates = <115200 115200 100>;};uartg: serial@c290000 {compatible = "nvidia,tegra186-hsuart";#stream-id-cells = <1>;reg = <0x0 0xc290000 0x0 0x40>;reg-shift = <2>;interrupts = <0 TEGRA186_IRQ_UARTG 0x04>;nvidia,memory-clients = <14>;dmas = <&gpcdma 2>, <&gpcdma 2>;dma-names = "rx", "tx";clocks = <&tegra_car TEGRA186_CLK_UARTG>,<&tegra_car TEGRA186_CLK_PLLP_OUT0>;clock-names = "serial", "parent";resets = <&tegra_car TEGRA186_RESET_UARTG>;reset-names = "serial";status = "disabled";nvidia,adjust-baud-rates = <115200 115200 100>;};combined-uart {compatible = "nvidia,tegra186-combined-uart";reg = <0x0 0x3c10000 0x0 0x4 /* TOP0_HSP_SM_0_1_BASE */0x0 0xc168000 0x0 0x4 /* AON_HSP_SM_1_BASE */0x0 0x3c00000 0x0 0x1000>; /* TOP0_HSP_COMMON_BASE */interrupts = <0 120 0x04>;status = "okay";};
};
2.2 别名定义
aliases {serial0 = &uarta;serial1 = &uartb;serial2 = &uartc;serial3 = &uartd;serial4 = &uarte;serial5 = &uartf;serial6 = &uartg;
2.3 中断配置
sources/hardware/nvidia/soc/t18x/kernel-include/dt-bindings/interrupt/tegra186-irq.h
#define TEGRA186_IRQ_UARTA 112
#define TEGRA186_IRQ_UARTB 113
#define TEGRA186_IRQ_UARTC 114
#define TEGRA186_IRQ_UARTD 115
#define TEGRA186_IRQ_UARTE 116
#define TEGRA186_IRQ_UARTF 117
#define TEGRA186_IRQ_UARTG 118
2.4 时钟配置
sources/hardware/nvidia/soc/t18x/kernel-dts/tegra186-soc/tegra186-soc-base.dtsitegra_car: clock@5000000 {compatible = "nvidia,tegra18x-car";reg = <0x0 0x05000000 0x0 0x01000000>;#clock-cells = <1>;#reset-cells = <1>;status = "disabled";
};
#define TEGRA186_CLK_UARTA 55
#define TEGRA186_CLK_UARTB 56
#define TEGRA186_CLK_UARTC 215
#define TEGRA186_CLK_UARTD 77
#define TEGRA186_CLK_UARTE 194
#define TEGRA186_CLK_UARTF 195
#define TEGRA186_CLK_UARTG 216#define TEGRA186_CLK_PLLP_OUT0 269
nvidia/soc/t18x/kernel-include/dt-bindings/reset/tegra186-reset.h:
#define TEGRA186_RESET_UARTA 47
#define TEGRA186_RESET_UARTB 48
#define TEGRA186_RESET_UARTC 49
#define TEGRA186_RESET_UARTD 50
#define TEGRA186_RESET_UARTE 132
#define TEGRA186_RESET_UARTF 111
#define TEGRA186_RESET_UARTG 112
2.5 默认串口配置
sources/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-common.dtsi
serial@3100000 {compatible = "nvidia,tegra20-uart", "nvidia,tegra186-hsuart";console-port;sqa-automation-port;status = "okay";};serial@3110000 {compatible = "nvidia,tegra186-hsuart";status = "okay";};serial@c280000 {compatible = "nvidia,tegra186-hsuart";status = "okay";};serial@3130000 {compatible = "nvidia,tegra186-hsuart";dma-names = "tx";status = "okay";};
2.6 添加串口
添加串口ttyTHS4、ttyTHS5、ttyTHS6，注意：ttyTHS4、ttyTHS5的引脚是和其它复用的，尽量别用
sources/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-common.dtsi ：
serial@3140000 {compatible = "nvidia,tegra186-hsuart";dma-names = "tx";status = "okay";};serial@3150000 {compatible = "nvidia,tegra186-hsuart";dma-names = "tx";status = "okay";};serial@c290000 {compatible = "nvidia,tegra186-hsuart";dma-names = "tx";status = "okay";};
3、引脚
| 序号 | 地址 | 设备名 | 寄存器名 | 收发引脚 | 引脚名称 | 设备树 |
|---|---|---|---|---|---|---|
| 1 | serial@3100000 | ttyS0 | UARTA | G12、H12 | UART0_* | 已配置 |
| 2 | serial@3110000 | ttyTHS1 | UARTB | B15、B16 | UART2_* | 已配置 |
| 3 | serial@c280000 | ttyTHS2 | UARTC | D10、D9 | UART1_* | 已配置 |
| 4 | serial@3130000 | ttyTHS3 | UARTD | H9、H10 | UART3_* | 已配置 |
| 5 | serial@3140000 | ttyTHS4 | UARTE | ？、B17 | FAN_TACH | 未配置 |
| 6 | serial@3150000 | ttyTHS5 | UARTF | B26、F20 | LCD_VDD_EN | 未配置 |
| 7 | serial@c290000 | ttyTHS6 | UARTG | D5、D8 | UART7 | 未配置 |
相关手册查询记录：
4、系统中关于串口的信息
4.1 设备挂载信息
root@tegra-ubuntu:/sys/bus/platform/devices# ls *serial -l
lrwxrwxrwx 1 root root 0 3月 21 14:35 3100000.serial -> …/…/…/devices/3100000.serial
lrwxrwxrwx 1 root root 0 3月 21 14:35 3110000.serial -> …/…/…/devices/3110000.serial
lrwxrwxrwx 1 root root 0 3月 21 14:35 3130000.serial -> …/…/…/devices/3130000.serial
lrwxrwxrwx 1 root root 0 3月 21 14:35 c280000.serial -> …/…/…/devices/c280000.serial
4.2 地址和设备文件名的对应关系
/sys/devices/3100000.serial/tty/ttyS0
/sys/devices/3110000.serial/tty/ttyTHS1
/sys/devices/c280000.serial/tty/ttyTHS2
/sys/devices/3130000.serial/tty/ttyTHS3
4.3 查看ttyS0
root@tegra-ubuntu:/sys/devices/3100000.serial/tty/ttyS0# ls
close_delay closing_wait custom_divisor dev device flags iomem_base iomem_reg_shift io_type irq line port power rt_flush rx_trig_bytes subsystem type uartclk uevent xmit_fifo_size
# cat close_delay // 关闭端口时的等待时间
50
# cat closing_wait // 关闭前输出发送的延迟
3000
# cat custom_divisor
0
# cat dev
4:64
# cat flags // 用户TTY标志(ASYNC_)
0xB9000000
# cat iomem_base
0x3100000
# cat iomem_reg_shift
2
# cat io_type
2
# cat irq
37
# cat line
0
# cat port
0x0
# cat rt_flush
0
# cat rx_trig_bytes
4
# cat type
20
# cat uartclk
408000000
# cat uevent
MAJOR=4
MINOR=64
DEVNAME=ttyS0
# cat xmit_fifo_size
32
4.4 查看ttyTHS1
root@tegra-ubuntu:/sys/devices/3110000.serial/tty/ttyTHS1# ls
close_delay closing_wait custom_divisor dev device flags iomem_base iomem_reg_shift io_type irq line port power rt_flush subsystem type uartclk uevent xmit_fifo_size
# cat close_delay
50
# cat closing_wait
3000
# cat custom_divisor
0
# cat dev
238:1
# cat flags
0x0
# cat iomem_base
0x3110000
# cat iomem_reg_shift
2
# cat io_type
3
# cat irq
38
# cat line
1
# cat port
0x0
# cat rt_flush
0
# cat type
20
# cat uartclk
0
# cat uevent
MAJOR=238
MINOR=1
DEVNAME=ttyTHS1
# cat xmit_fifo_size
32
4.5 查看ttyTHS2
root@tegra-ubuntu:/sys/devices/c280000.serial/tty/ttyTHS2# ls
close_delay closing_wait custom_divisor dev device flags iomem_base iomem_reg_shift io_type irq line port power rt_flush subsystem type uartclk uevent xmit_fifo_size
# cat close_delay
50
# cat closing_wait
3000
# cat custom_divisor
0
# cat dev
238:2
# cat flags
0x0
# cat iomem_base
0xC280000
# cat iomem_reg_shift
2
# cat io_type
3
# cat irq
39
# cat line
2
# cat port
0x0
# cat rt_flush
0
# cat type
20
# cat uartclk
0
# cat uevent
MAJOR=238
MINOR=2
DEVNAME=ttyTHS2
# cat xmit_fifo_size
32
4.6 查看ttyTHS3
root@tegra-ubuntu:/sys/devices/3130000.serial/tty/ttyTHS3# ls
close_delay closing_wait custom_divisor dev device flags hci0 iomem_base iomem_reg_shift io_type irq line port power rt_flush subsystem type uartclk uevent xmit_fifo_size
# cat close_delay
50
# cat closing_wait
3000
# cat custom_divisor
0
# cat dev
238:3
# cat flags
0x0
# cat iomem_base
0x3130000
# cat iomem_reg_shift
2
# cat io_type
3
# cat irq
40
# cat line
3
# cat port
0x0
# cat rt_flush
0
# cat type
20
# cat uartclk
0
# cat uevent
MAJOR=238
MINOR=3
DEVNAME=ttyTHS3
# cat xmit_fifo_size
32
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