typedef struct {int counter;
} atomic_t;

#define ATOMIC_INIT(i)    { (i) }----------------------------------声明一个原子变量并初始化为i。#define atomic_read(v)    ACCESS_ONCE((v)->counter)----------------读取原子变量的值。
#define atomic_set(v,i)    (((v)->counter) = (i))------------------设置变量v的值为i。#define atomic_xchg(v, new) (xchg(&((v)->counter), new))-----------把new赋值给原子变量v，返回原子变量v的旧值。#define atomic_cmpxchg---------------------------------------------比较old和原子变量v的值，如果相等则把new赋值给v，返回原子变量v的旧值。#define atomic_inc(v)        atomic_add(1, v)----------------------原子地给v加1
#define atomic_dec(v)        atomic_sub(1, v)----------------------原子地给v减1#define atomic_inc_and_test(v)    (atomic_add_return(1, v) == 0)---原子地给v加1，并且返回最新v的值
#define atomic_dec_and_test(v)    (atomic_sub_return(1, v) == 0)---原子地给v减1，并且返回最新v的值
#define atomic_inc_return(v)    (atomic_add_return(1, v))----------原子地给v加1，结果为0返回true，否则返回false。
#define atomic_dec_return(v)    (atomic_sub_return(1, v))----------原子地给v减1，结果为0返回true，否则返回fasle。
#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)---原子地给v减i，结果为0返回true，否则返回false。#define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)

#define ATOMIC_OPS(op, c_op, asm_op)                    \ATOMIC_OP(op, c_op, asm_op)                    \ATOMIC_OP_RETURN(op, c_op, asm_op)ATOMIC_OPS(add, +=, add)
ATOMIC_OPS(sub, -=, sub)#define ATOMIC_OP(op, c_op, asm_op)                    \
static inline void atomic_##op(int i, atomic_t *v)            \
{                                    \unsigned long tmp;                        \int result;                            \\prefetchw(&v->counter);                        \----------------------提前把原子变量的值加载到cache中，以便提高性能。__asm__ __volatile__("@ atomic_" #op "\n"            \
"1:    ldrex    %0, [%3]\n"                        \----------------------ldrex指令把原子变量v->counter的值加载到result变量中，然后在result变量中增加i值，使用strex指令把result变量的值存放到原子变量v->result中，其中变量tmp保存着strex指令更新后的结果。
"    " #asm_op "    %0, %0, %4\n"                    \
"    strex    %1, %0, [%3]\n"                        \
"    teq    %1, #0\n"                        \
"    bne    1b"                            \: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)        \: "r" (&v->counter), "Ir" (i)                    \--------------------最后比较该结果是否为0，为0则表示strex指令更新成功。如果不为0，那么跳转到标签“1”处重新再来一次。: "cc");                            \
}                                    \#define ATOMIC_OP_RETURN(op, c_op, asm_op)                \
static inline int atomic_##op##_return(int i, atomic_t *v)        \
{                                    \unsigned long tmp;                        \int result;                            \\smp_mb();                            \prefetchw(&v->counter);                        \\__asm__ __volatile__("@ atomic_" #op "_return\n"        \
"1:    ldrex    %0, [%3]\n"                        \
"    " #asm_op "    %0, %0, %4\n"                    \
"    strex    %1, %0, [%3]\n"                        \
"    teq    %1, #0\n"                        \
"    bne    1b"                            \: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)        \: "r" (&v->counter), "Ir" (i)                    \: "cc");                            \\smp_mb();                            \\return result;                            \
}

static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
{extern void __bad_xchg(volatile void *, int);unsigned long ret;
#ifdef swp_is_buggyunsigned long flags;
#endif
#if __LINUX_ARM_ARCH__ >= 6unsigned int tmp;
#endifsmp_mb();prefetchw((const void *)ptr);switch (size) {
#if __LINUX_ARM_ARCH__ >= 6case 1:asm volatile("@    __xchg1\n""1:    ldrexb    %0, [%3]\n""    strexb    %1, %2, [%3]\n""    teq    %1, #0\n""    bne    1b": "=&r" (ret), "=&r" (tmp): "r" (x), "r" (ptr): "memory", "cc");break;case 4:asm volatile("@    __xchg4\n""1:    ldrex    %0, [%3]\n""    strex    %1, %2, [%3]\n""    teq    %1, #0\n""    bne    1b": "=&r" (ret), "=&r" (tmp): "r" (x), "r" (ptr): "memory", "cc");break;
#elif defined(swp_is_buggy)
#ifdef CONFIG_SMP
#error SMP is not supported on this platform
#endifcase 1:raw_local_irq_save(flags);ret = *(volatile unsigned char *)ptr;*(volatile unsigned char *)ptr = x;raw_local_irq_restore(flags);break;case 4:raw_local_irq_save(flags);ret = *(volatile unsigned long *)ptr;*(volatile unsigned long *)ptr = x;raw_local_irq_restore(flags);break;
#elsecase 1:asm volatile("@    __xchg1\n""    swpb    %0, %1, [%2]": "=&r" (ret): "r" (x), "r" (ptr): "memory", "cc");break;case 4:asm volatile("@    __xchg4\n""    swp    %0, %1, [%2]": "=&r" (ret): "r" (x), "r" (ptr): "memory", "cc");break;
#endifdefault:__bad_xchg(ptr, size), ret = 0;break;}smp_mb();return ret;
}#define xchg(ptr,x) \((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
{int oldval;unsigned long res;smp_mb();prefetchw(&ptr->counter);do {__asm__ __volatile__("@ atomic_cmpxchg\n""ldrex    %1, [%3]\n""mov    %0, #0\n""teq    %1, %4\n""strexeq %0, %5, [%3]\n": "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter): "r" (&ptr->counter), "Ir" (old), "r" (new): "cc");} while (res);smp_mb();return oldval;
}

#define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory")
#define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory")
#define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory")#define mb()        do { dsb(); outer_sync(); } while (0)
#define rmb()        dsb()
#define wmb()        do { dsb(st); outer_sync(); } while (0)--------------------------------ST：DSB operation that waits only for stores to complete#define smp_mb()    dmb(ish)----------------------------------------------------------------ISH：DMB operation only to the inner shareable domain
#define smp_rmb()    smp_mb()
#define smp_wmb()    dmb(ishst)-------------------------------------------------------------ISHST:DMB operation that waits only for stores to complete, and only to the inner shareable domain#define smp_read_barrier_depends()    do { } while(0)

static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,struct net_device *dev)
{
.../* Note: the chip doesn't have auto-pad! */if (likely(len < TX_BUF_SIZE)) {if (len < ETH_ZLEN)memset(tp->tx_buf[entry], 0, ETH_ZLEN);skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);dev_kfree_skb_any(skb);} else {dev_kfree_skb_any(skb);dev->stats.tx_dropped++;return NETDEV_TX_OK;}spin_lock_irqsave(&tp->lock, flags);/** Writing to TxStatus triggers a DMA transfer of the data* copied to tp->tx_buf[entry] above. Use a memory barrier* to make sure that the device sees the updated data.*/wmb();------------------------------------------------------------------确保之前的数据已经进入buffer，将buffer操作和DMA操作隔开。RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
...
}

#define set_current_state(state_value)            \set_mb(current->state, (state_value))#define set_mb(var, value)    do { var = value; smp_mb(); } while (0)--------------此处smp_mb()确保current->state的值已经得到更新。

static inline void __set_task_cpu(struct task_struct *p, unsigned int cpu)
{set_task_rq(p, cpu);
#ifdef CONFIG_SMP/** After ->cpu is set up to a new value, task_rq_lock(p, ...) can be* successfuly executed on another CPU. We must ensure that updates of* per-task data have been completed by this moment.*/smp_wmb();-----------------------------------确保之前的的写操作已经得到更新。task_thread_info(p)->cpu = cpu;p->wake_cpu = cpu;
#endif
}