Part 1 Cache

An Overview of Cache Principles

1.1 Caches, ‘Caches,’ and “Caches”

1.2 Locality Principles

1.2.1 Temporal Locality

1.2.2 Spatial Locality

1.2.3 Algorithmic Locality

1.2.4 Geographical Locality? Demographical Locality?

1.3 What to Cache, Where to Put It, and How to Maintain It

1.3.1 Logical Organization Basics: Blocks, Tags, Sets

1.3.2 Content Management: To Cache or Not to Cache

1.3.3 Consistency Management: Its Responsibilities 一致性管理：其职责

• Keep the Cache Consistent with Itself 保持缓存与自身一致
• Keep the Cache Consistent with the Backing Store 保持缓存与备份存储保持一致
• Keep the Cache Consistent with Other Caches

1.3.4 Inclusion and Exclusion

1.4 Insights and Optimizations 见解和优化

1.4.1 Perspective 工程视角

• Reconsidering Bandwidth and Block Size: DSP Caches 重新调整带宽和块大小：DSP缓存
• Reconsidering Permanent Store: Plan 9’s File System 重新考虑永久存储区：计划9的文件系统

1.4.2 Important Issues, Future Directions

第二章 Logical Organization 逻辑结构

2.1 Logical Organization: A Taxonomy 逻辑组织：A分类法

2.2 Transparently Addressed Caches 透明地址高速缓存

2.2.1 Implicit Management: Transparent Caches 隐式管理：透明的高速缓存

2.2.2 Explicit Management: Software-Managed Caches 显式管理：由软件管理的缓存

• VMP: Software-Controlled Virtual Caches
• SoftVM: A Cache-Fill Instruction

2.3 Non-Transparently Addressed Caches

2.3.1 Explicit Management: Scratch-Pad Memories 显式管理：便笺式存储器

• Perspective: Embedded vs. General-Purpose Systems 观点：嵌入式与通用系统

2.3.2 Implicit Management: Self-Managed Scratch-Pads 隐式管理：自我管理的便笺式存储器

2.4 Virtual Addressing and Protection

2.4.1 Virtual Caches

2.4.2 ASIDs and Protection Bits

2.4.3 Inherent Problems 固有的问题

2.5 Distributed and Partitioned Caches 分布式和分区的高速缓存

2.5.1 UMA and NUMA

2.5.2 COMA

2.5.3 NUCA and NuRAPID

2.5.4 Web Caches

• Client-Side Web Caches
• Server-Side Web Caches

2.5.5 Buffer Caches

2.6 Case Studies

2.6.1 A Horizontal-Exclusive Organization: Victim Caches, Assist Caches

2.6.2 A Software Implementation: BSD’s Buffer Cache

• A Set-Associative Software-Managed Cache
• A Dynamically Defi ned Cache Block

2.6.3 Another Dynamic Cache Block: Trace Caches

• VLIW and the Instruction-Fetch Problem
• Tree-VLIW Instructions
• The Fill Unit
• Multi-Branch Predictor and Branch-Address Cache
• The Shadow Cache
• A Range of Fetch and Align Strategies
• The Patented Design 获得专利的cache
• The “Trace Cache”

第3章 Management of Cache Contents

3.1 Case Studies: On-Line Heuristics

3.1.1 On-Line Partitioning Heuristics 在线分区启发式

• Replacement Strategies 替换策略
• Other Policies and Strategies for Transparent (Processor) Caches
• Jouppi’s Victim Cache, HP-7200 Assist Cache
• McFarling’s Dynamic Exclusion
• Tyson’s Modifi ed Approach
• Rivers’ Non-Temporal Streaming Cache
• Johnson’s Frequency Tracking 约翰逊的频率跟踪
• Lee’s Region-Based Division 李氏区域部门
• On-Line Low-Power Schemes: Kaxiras’ Cache Decay 在线低功耗方案：Kaxiras的高速缓存衰减

3.1.2 On-Line Prefetching Heuristics1 在线预取启发式方法1

• Prefetching Instructions, i.e., Branch Prediction
• Early Work in Prefetching Sequential Data Accesses
• Jouppi’s Stream Buffers
• Baer’s Reference Prediction Table: Stride Prefetching 贝尔的参考预测表：字符串预取
• Palacharla’s Elimination of the Program Counter 帕拉查拉的消除项目计数器
• Prefetching Non-Stride Accesses 正在预取非字符串的访问权限
• Ramamoorthy’s Look-ahead Unit: Continual Optimization in 1966 拉马莫尔西的前瞻性单元：1966年的持续优化
• Correlation Prefetching in Processor Caches 处理器缓存中的相关性预取
• Correlation Prefetching in File Caches: Overcoming State-Table Limits 文件缓存中的相关预取：超越状态表限制
• Content-Based Prefetching 基于内容的预取

3.1.3 On-Line Locality Optimizations

• Dynamic (Re-)Grouping of Instructions and Data 指令和数据的动态（重新）分组
• Page Coloring and Careful Mappping 页面着色和仔细的映射
• Dynamic Compression of Instructions and Data 指令和数据的动态压缩
• Brooks’ Dynamic Adjustment of Data Width 布鲁克斯对数据宽度的动态调整
• Dynamic Reordering of Memory Requests 内存请求的动态重新排序

3.2 Case Studies: Off-Line Heuristics

3.2.1 Off-Line Partitioning Heuristics

• Programmer-Directed Partition Assignment 程序员定向分配
• Farrahi’s Partitioning for Sleep Mode Farrahi对睡眠模式的分区
• Static Scratch-Pad Management: Panda, Banakar 静态便签式高速缓存管理
• Dynamic Scratch-Pad Management: Cooper, Kandemir, Udayakumaran 动态便签式高速缓存管理

3.2.2 Off-Line Prefetching Heuristics

• Architectural Support
• Mowry’s Algorithm
• Support for Indexed Arrays 支持索引阵列
• Pointer Prefetching 指针预取
• Natural Pointer Techniques 自然指针技术
• Jump Pointer Techniques 跳跃指针技术

3.2.3 Off-Line Locality Optimizations

• Ramamoorthy’s Connectivity and Reachability Matrices 拉马莫尔西的连通性和可达性矩阵
• Lowe’s Incorporation of Data and a Notion of Time 劳的数据整合和时间的概念

3.3 Case Studies: Combined Approaches

3.3.1 Combined Approaches to Partitioning 进行分区的组合方法

• HPL-PD, PlayDoh v1.1 — General Architecture
• Abraham’s Profi le-Directed Partitioning 亚伯拉罕的个人定向划分
• Hardware/Software Memory Disambiguation 硬件/软件内存消除歧义

3.3.2 Combined Approaches to Prefetching 预取的组合方法

• Pipelined Vector Computers 管道式向量式计算机
• An Argument for Application-Directed File Caches 针对应用程序定向的文件缓存的一个参数
• Cao’s Application-Controlled File Caching 曹的应用程序控制的文件缓存
• Patterson’s Informed Prefetching and Caching 帕特森的信息预取和缓存
• A Note on Prefetching and Caching关于预取和缓存的说明

3.3.3 Combined Approaches to Optimizing Locality

• Hatfi eld and Gerald’s Program Restructuring 哈特菲·赫尔德和杰拉尔德的项目重组
• Interlude: The Importance of Considering Time 插曲：考虑时间的重要性
• Ferrari’s Critical Working Sets 法拉利的关键工作集
• McFarling’s Instruction Cache Optimization 麦克法林的指令缓存优化
• Hwu and Chang’s Optimizing Compiler 武和张的优化编译器
• Pettis and Hansen’s Profi le-Guided Positioning 佩蒂斯和汉森的专业导向定位
• Gloy’s Temporal Ordering Information
• Zorn’s Lifetime-Conscious Heap Management Zorn的终身意识堆堆管理
• Calder’s Cache-Conscious Data Placement 考尔德的具有高速缓存意识的数据放置
• Chilimbi’s Cache-Conscious Structure Layout Chilimbi的缓存意识结构布局
• DRAM Address Mappings

3.4 Discussions

3.4.1 Proposed Scheme vs. Baseline

3.4.2 Prefetching vs. Locality Optimizations

3.4.3 Application-Directed Management vs. Transparent Management

3.4.4 Real Time vs. Average Case

3.4.5 Naming vs. Cache Conflicts

3.4.6 Dynamic vs. Static Management

3.5 Building a Content-Management Solution 内容管理的解决方案

3.5.1 Degree of Dynamism 活力度

• Static Decision
• Dynamic Decision

3.5.2 Degree of Prediction 预测度

• Reactive Scheme
• Proactive Scheme 主动式设计方案
• Speculative Scheme 投机方案

3.5.3 Method of Classification 分类方法

3.5.4 Method for Ensuring Availability 确保可用性的方法

• Data- and Algorithm-Oriented Operations 面向数据和算法的操作
• Name-Oriented Operations 面向名称的操作
• Request-Oriented Operations 面向请求的操作

第4章 Management of Cache Consistency

4.1 Consistency with Backing Store

4.1.1 Write-Through

4.1.2 Delayed Write, Driven By the Cache

• Conflict-Driven Update
• Capacity-Driven Update
• Timer-Driven Update
• Power-Driven Update

4.1.3 Delayed Write, Driven by Backing Store

4.2 Consistency with Self

4.2.1 Virtual Cache Management

• The Consistency Problem of Virtual Caches
• Perspective on Aliasing
• Virtual Caches and the Protection Problem

4.2.2 ASID Management

4.3 Consistency with Other Clients

4.3.1 Motivation, Explanation, Intuition 动机、解释、直觉

• Scenario One
• An Analogy: Distributed Systems Design
• In Particular, Cache Systems

4.3.2 Coherence vs. Consistency

4.3.3 Memory-Consistency Models

• Sequential Consistency
• Processor Consistency
• Other Consistency Models

4.3.4 Hardware Cache-Coherence Mechanisms

• Cache Block States
• Using Write-Through Caches (SI)
• Using Write-Back Caches (MSI)
• Reducing Write Broadcasts (MESI)
• Distributing Control (MOESI)
• Cache Organization Issues
• Interconnect Options and Their Ramifi cations 互连选项和他们的拉米菲阳离子
• Snoopy Protocols
• Directory-Based Protocols
• Perspective on the Coherence Point

4.3.5 Software Cache-Coherence Mechanisms

• Ivy
• Munin
• Midway
• TreadMarks

第5章 Implementation Issues

5.1 Overview

5.2 SRAM Implementation

5.2.1 Basic 1-Bit Memory Cell

• Physical Implementation of the 1-Bit Memory Cell
• Transistor Sizing 晶体管的尺寸测定
• Soft Error Rate (SER) 软错误率(SER)

5.2.2 Address Decoding

• Predecoding
• Row and Column Decoding
• Non-Partitioned
• Divided Wordline (DWL)
• Hierarchical Word Decoding (HWD)
• Pulsed Wordline 脉冲波谱线

5.2.3 Physical Decoder Implementation

• Digital Logic Styles
• Domino Dynamic Logic

5.2.4 Peripheral Bitline Circuits 外围设备的位线电路

• Precharge and Equalize Circuits 预充电和均衡的电路
• Read and Write Multiplexers 读写多路复用器

5.2.5 Sense Amplifiers

• Physical Implementation
• Sensing Hierarchy

5.2.6 Write Amplifier

5.2.7 SRAM Partitioning

5.2.8 SRAM Control and Timing

5.2.9 SRAM Interface

5.3 Advanced SRAM Topics

5.3.1 Low-Leakage Operation 低泄漏操作

• Multi-Vt Memory Cells
• Gated-Vdd Technique 门控式vdd
• Gated-Ground Technique
• Drowsy SRAMs

5.4 Cache Implementation

5.4.1 Simple Caches

5.4.2 Processor Interfacing

5.4.3 Multiporting 多重数据移植技术

第6章 Cache Case Studies

6.1 Logical Organization

6.1.1 Motorola MPC7450

6.1.2 AMD Opteron

6.1.3 Intel Itanium-2

6.2 Pipeline Interface

6.2.1 Motorola MPC7450

6.2.2 AMD Opteron

6.2.3 Intel Itanium-2

6.3 Case Studies of Detailed Itanium-2 Circuits

6.3.1 L1 Cache RAM Cell Array

6.3.2 L2 Array Bitline Structure

6.3.3 L3 Subarray Implementation

6.3.4 Itanium-2 TLB and CAM Implementation

part2 memory

第7章 Overview of DRAMs

7.1 DRAM Basics: Internals, Operation

7.2 Evolution of the DRAM Architecture DRAM架构的演变

7.2.1 Structural Modifi cations Targeting Throughput

• Clocked DRAM
• The Conventional Asynchronous DRAM
• Fast Page Mode DRAM (FPM DRAM)
• Extended Data-Out DRAM (EDO DRAM)
• Burst-Mode EDO DRAM (BEDO DRAM)
• IBM’s High-Speed Toggle Mode DRAM
• Synchronous DRAM (SDRAM)

7.2.2 Interface Modifications Targeting Throughput

• Rambus DRAM (RDRAM, Concurrent RDRAM, and Direct RDRAM)
• Double Data Rate DRAM (DDR SDRAM)

7.2.3 Structural Modifications Targeting Latency

• Virtual Channel Memory (VCDRAM)
• Enhanced SDRAM (ESDRAM)
• MoSys 1T-SRAM
• Reduced Latency DRAM (RLDRAM)
• Fast Cycle DRAM (FCRAM)

7.2.4 Rough Comparison of Recent DRAMs

7.3 Modern-Day DRAM Standards

7.3.1 Salient Features of JEDEC’s SDRAM Technology JEDEC sdram技术的显著特点

• Single Data Rate SDRAM
• Double Data Rate SDRAM

7.3.2 Other Technologies, Rambus in Particular 其他技术，尤其是匝道

• Rambus’ ’898 Patent Application

7.3.3 Comparison of Technologies in Rambus and JEDEC DRAM Rambus与JEDECDRAM中的技术比较

• Programmable CAS Latency
• Programmable Burst Length
• Dual-Edged Clocking
• On-Chip PLL/DLL

7.3.4 Alternative Technologies

• Programmable CAS Latency
• Programmable Burst Length
• Dual-Edged Clocking
• On-Chip PLL/DLL

7.4 Fully Buffered DIMM: A Compromise of Sorts 完全缓冲的DIMM：一种妥协

7.5 Issues in DRAM Systems, Briefly DRAM系统中的5个问题，简要介绍

7.5.1 Architecture and Scaling

7.5.2 Topology and Timing

7.5.3 Pin and Protocol Efficiency 插销和协议的有效率

7.5.4 Power and Heat Dissipation

7.5.5 Future Directions

第8章 DRAM Device Organization: Basic Circuits and Architecture

8.1 DRAM Device Organization

8.2 DRAM Storage Cells

8.2.1 Cell Capacitance, Leakage, and Refresh 单元格电容、泄漏和刷新

8.2.2 Confl icting Requirements Drive Cell Structure

8.2.3 Trench Capacitor Structure 沟槽电容器结构

8.2.4 Stacked Capacitor Structure 堆叠式电容器结构

8.3 RAM Array Structures

8.3.1 Open Bitline Array Structure

8.3.2 Folded Bitline Array Structure

8.4 Differential Sense Amplifier 差分感知放大器

8.4.1 Functionality of Sense Amplifiers in DRAM Devices

8.4.2 Circuit Diagram of a Basic Sense Amplifier 一个基本传感放大器的电路图

8.4.3 Basic Sense Amplifi er Operation 基本感知放大器操作

8.4.4 Voltage Waveform of Basic Sense Amplifier Operation 基本感应放大器操作的电压波形

8.4.5 Writing into DRAM Array

8.5 Decoders and Redundancy 解码器和冗余度

8.5.1 Row Decoder Replacement Example

8.6 DRAM Device Control Logic

8.6.1 Synchronous vs. Non-Synchronous

8.6.2 Mode Register-Based Programmability 基于模式寄存器的可编程性

8.7 DRAM Device Configuration

8.7.1 Device Configuration Trade-offs

8.8 Data I/O

8.8.1 Burst Lengths and Burst Ordering

8.8.2 N-Bit Prefetch

8.9 DRAM Device Packaging

8.10 DRAM Process Technology and Process Scaling Considerations DRAM工艺技术和工艺缩放考虑事项

8.10.1 Cost Considerations

8.10.2 DRAM- vs. Logic-Optimized Process Technology DRAM与逻辑优化工艺技术

第9章 DRAM System Signaling and Timing DRAM系统信号和定时

9.1 Signaling System 信号发送系统

9.2 Transmission Lines on PCBs PCB上的2条输电线路

9.2.1 Brief Tutorial on the Telegrapher’s Equations 关于电报员方程式的简要教程

9.2.2 RC and LC Transmission Line Models RC和LC输电线路型号

9.2.3 LC Transmission Line Model for PCB Traces PCB痕迹的LC传输线路模型

9.2.4 Signal Velocity on the LC Transmission Line LC传输线路上的信号速度

9.2.5 Skin Effect of Conductors 导线的皮肤效应

9.2.6 Dielectric Loss 电介质损耗

9.2.7 Electromagnetic Interference and Crosstalk 电磁干扰和串扰干扰

9.2.8 Near-End and Far-End Crosstalk 近端和远端串扰

9.2.9 Transmission Line Discontinuities 输电线路的不连续性

9.2.10 Multi-Drop Bus 多滴式总线

9.2.11 Socket Interfaces

9.2.12 Skew 倾斜度

9.2.13 Jitter 搅拌器

9.2.14 Inter-Symbol Interference (ISI) 符号间干扰(ISI)

9.3 Termination

9.3.1 Series Stub (Serial) Termination 系列螺柱（串行）终止

9.3.2 On-Die (Parallel) Termination在模（平行）终止

9.4 Signaling

9.4.1 Eye Diagrams

9.4.2 Low-Voltage TTL (Transistor-Transistor Logic) 低压TTL（晶体管-晶体管逻辑）

9.4.3 Voltage References 电压参考

9.4.4 Series Stub Termination Logic 系列螺柱终止逻辑

9.4.5 RSL and DRSL

9.5 Timing Synchronization 定时同步

9.5.1 Clock Forwarding时钟转发

9.5.2 Phase-Locked Loop (PLL) 锁相回路(PLL)

9.5.3 Delay-Locked Loop (DLL) 延迟锁定环路(DLL)

9.6 Selected DRAM Signaling and Timing Issues 选定的DRAM信号和定时问题

9.6.1 Data Read and Write Timing in DDRx SDRAM Memory Systems DDRx sdram内存系统中的数据读写时间

9.6.2 The Use of DLL in DDRx SDRAM Devices

9.6.3 The Use of PLL in XDR DRAM Devices

9.7 Summary

第10章 DRAM Memory System Organization

10.1 Conventional Memory System

10.2 Basic Nomenclature 基本术语

10.2.1 Channel

10.2.2 Rank

10.2.3 Bank

10.2.4 Row

10.2.5 Column

10.2.6 Memory System Organization: An Example

10.3 Memory Modules

10.3.1 Single In-line Memory Module (SIMM) 单个联机内存模块(SIMM)

10.3.2 Dual In-line Memory Module (DIMM)

10.3.3 Registered Memory Module (RDIMM)

10.3.4 Small Outline DIMM (SO-DIMM)

10.3.5 Memory Module Organization

10.3.6 Serial Presence Detect (SPD)

10.4 Memory System Topology

10.4.1 Direct RDRAM System Topology

10.5 Summary

第11章 Basic DRAM Memory-Access Protocol

11.1 Basic DRAM Commands

11.1.1 Generic DRAM Command Format 通用DRAM命令格式

11.1.2 Summary of Timing Parameters 定时参数汇总表

11.1.3 Row Access Command

11.1.4 Column-Read Command

11.1.5 Column-Write Command

11.1.6 Precharge Command

11.1.7 Refresh Command

11.1.8 A Read Cycle

11.1.9 A Write Cycle

11.1.10 Compound Commands 复合命令

11.2 DRAM Command Interactions

11.2.1 Consecutive Reads and Writes to Same Rank 连续阅读和写入同一rank

11.2.2 Read to Precharge Timing

11.2.3 Consecutive Reads to Different Rows of Same Bank 连续阅读同一银行的不同行

• Best-Case Scenario
• Worst-Case Scenario

11.2.4 Consecutive Reads to Different Banks: Bank Conflict

• Without Command Reordering
• With Command Reordering

11.2.5 Consecutive Read Requests to Different Ranks

11.2.6 Consecutive Write Requests: Open Banks 连续写入请求：open bank

11.2.7 Consecutive Write Requests: Bank Conflicts 连续写请求：

11.2.8 Write Request Following Read Request: Open Banks

11.2.9 Write Request Following Read Request to Different Banks, Bank Confl ict, Best Case, No Reordering

11.2.10 Read Following Write to Same Rank, Open Banks

11.2.11 Write to Precharge Timing

11.2.12 Read Following Write to Different Ranks, Open Banks

11.2.13 Read Following Write to Same Bank, Bank Conflict

11.2.14 Read Following Write to Different Banks of Same Rank, Bank Confl ict, Best Case, No Reordering

11.2.15 Column-Read-and-Precharge Command Timing

11.2.16 Column-Write-and-Precharge Timing

11.3 Additional Constraints

11.3.1 Device Power Limit

11.3.2 tRRD: Row-to-Row (Activation) Delay

11.3.3 tFAW: Four-Bank Activation Window

11.3.4 2T Command Timing in Unbuffered Memory Systems

11.4 Command Timing Summary

11.5 Summary

第12章 Evolutionary Developments of DRAM Device Architecture

12.1 DRAM Device Families

12.1.1 Cost (Capacity), Latency, Bandwidth, and Power

12.2 Historical-Commodity DRAM Devices

12.2.1 The Intel 1103

12.2.2 Asynchronous DRAM Devices

12.2.3 Page Mode and Fast Page Mode DRAM (FPM DRAM)

12.2.4 Extended Data-Out (EDO) and Burst Extended Data-Out (BEDO) Devices

12.3 Modern-Commodity DRAM Devices

12.3.1 Synchronous DRAM (SDRAM)

• SDRAM-Access Protocol
• Die Photo and a TSOP Package
• PC100—The Proliferation of Extended, Rigorous DRAM Standardization and Qualifi cation Processes

12.3.2 Double Data Rate SDRAM (DDR SDRAM)

• DDR SDRAM-Access Protocol
• DDR SDRAM I/O Interface
• Series Stub Terminated Signaling Protocol

12.3.3 DDR2 SDRAM

12.3.4 Protocol and Architectural Differences

• Differential Strobes and FBGA Packages

12.3.5 DDR3 SDRAM

12.3.6 Scaling Trends of Modern-Commodity DRAM Devices

12.4 High Bandwidth Path

12.4.1 Direct RDRAM

• The Rambus Signaling Level (RSL)
• Memory System Architecture
• Device Architecture
• Topology
• Access Protocol
• The Write-to-Read Turnaround Issue
• Write Buffer in Direct RDRAM Devices

12.4.2 Technical and Pseudo-Technical Issues of Direct RDRAM

• Die Size Overhead
• Sophisticated System Engineering Requirement
• Advanced Packaging and Testing Equipment Requirement
• Heat Density—Heat Spreader—Enforced Idle Cycles
• Low Request Rate Systems
• Different Devices for Different Systems
• Lessons for Future Memory Systems

12.4.3 XDR Memory System

• Topology
• Device Architecture
• Signaling
• FlexPhase
• XDR Early Read After Write

12.5 Low Latency

12.5.1 Reduced Latency DRAM (RLDRAM)

12.5.2 Fast Cycle DRAM (FCRAM)

12.6 Interesting Alternatives

12.6.1 Virtual Channel Memory (VCDRAM)

12.6.2 Enhanced SDRAM (ESDRAM)

第13章 DRAM Memory Controller

13.1 DRAM Controller Architecture

13.2 Row-Buffer-Management Policy

13.2.1 Open-Page Row-Buffer-Management Policy

13.2.2 Close-Page Row-Buffer-Management Policy

13.2.3 Hybrid (Dynamic) Row-Buffer Management Policies

13.2.4 Performance Impact of Row-Buffer Management Policies

13.2.5 Power Impact of Row-Buffer Management Policies

13.3 Address Mapping (Translation)

13.3.1 Available Parallelism in Memory System Organization

• Channel
• Rank
• Bank
• Row
• Column

13.3.2 Parameter of Address Mapping Schemes

13.3.3 Baseline Address Mapping Schemes

• Open-Page Baseline Address Mapping Scheme
• Close-Page Baseline Address Mapping Scheme

13.3.4 Parallelism vs. Expansion Capability

13.3.5 Address Mapping in the Intel 82955X MCH

• Symmetric and Asymmetric Dual Channel Modes
• Address Mapping Confi guration Registers
• Per-Rank Address Mapping Schemes
• Quick Summary of Address Mapping in the 82955X MCH

13.3.6 Bank Address Aliasing (Stride Collision)

• Hardware Solution to the Address Aliasing Problem

13.4 Performance Optimization

13.4.1 Write Caching

13.4.2 Request Queue Organizations

13.4.3 Refresh Management

13.4.4 Agent-Centric Request Queuing Organization

13.4.5 Feedback-Directed Scheduling

13.5 Summary

第14章 The Fully Buffered DIMM Memory System

14.1 Introduction

14.2 Architecture

14.3 Signaling and Timing

14.3.1 Clock Data Recovery

14.3.2 Unit Interval

14.3.3 Resample and Resync

14.4 Access Protocol

14.4.1 Frame Definitions

• Southbound Command-Only Frame
• Southbound Command Plus (Write) Data Frame
• Northbound Data Frame

14.4.2 Command Definitions

14.4.3 Frame and Command Scheduling

14.5 The Advanced Memory Buffer

14.5.1 SMBus Interface

14.5.2 Built-In Self-Test (BIST)

14.5.3 Thermal Sensor

14.6 Reliability, Availability, and Serviceability

14.6.1 Checksum Protection in the Transport Layer

14.6.2 Bit Lane Steering Bit Lane转向

14.6.3 Fail-over Modes 故障切换模式

14.6.4 Hot Add and Replace

14.7 FB-DIMM Performance Characteristics

14.7.1 Fixed vs. Variable Latency Scheduling

14.8 Perspective

第15章 Memory System Design Analysis

15.1 Overview

15.2 Workload Characteristics

15.2.1 164.gzip: C Compression

15.2.2 176.gcc: C Programming Language Compiler

15.2.3 197.parser: C Word Processing

15.2.4 255.vortex: C Object-Oriented Database

15.2.5 172.mgrid: Fortran 77 Multi-Grid Solver: 3D Potential Field

15.2.6 SETI@HOME

15.2.7 Quake 3

15.2.8 178.galgel, 179.art, 183.equake, 188.ammp, JMark 2.0, and 3DWinbench

15.2.9 Summary of Workload Characteristics

15.3 The RAD Analytical Framework

15.3.1 DRAM-Access Protocol

15.3.2 Computing DRAM Protocol Overheads

15.3.3 Computing Row Cycle Time Constraints

15.3.4 Computing Row-to-Row Activation Constraint

15.3.5 Request Access Distance Efficiency Computation

15.3.6 An Applied Example for a Close-Page System

15.3.7 An Applied Example for an Open-Page System

15.3.8 System Confi guration for RAD-Based Analysis

15.3.9 Open-Page Systems: 164.gzip

15.3.10 Open-Page Systems: 255.vortex

15.3.11 Open-Page Systems: Average of All Workloads

15.3.12 Close-Page Systems: 164.gzip

15.3.13 Close-Page Systems: SETI@HOME Processor Bus Trace

15.3.14 Close-Page Systems: Average of All Workloads

15.3.15 tFAW Limitations in Open-Page System: All Workloads

15.3.16 Bandwidth Improvements: 8-Banks vs. 16-Banks

15.4 Simulation-Based Analysis

15.4.1 System Confi gurations

15.4.2 Memory Controller Structure

15.4.3 DRAM Command Scheduling Algorithms

• Bank Round-Robin (BRR)
• Rank Round-Robin
• Wang Rank Hop (Wang)
• Greedy 贪婪

15.4.4 Workload Characteristics

• Address Distribution
• Read Transaction Percentage
• Short Burst Request Percentage

15.4.5 Timing Parameters

15.4.6 Protocol Table

15.4.7 Queue Depth, Scheduling Algorithms, and Burst Length

15.4.8 Effect of Burst Length on Sustainable Bandwidth

15.4.9 Burst Chop in DDR3 SDRAM Devices

• Standard (STD) Burst Chop
• Short Write Burst Bank Switching (WBS) 短写突发银行开关(WBS)
• Short Read Burst and Short Write Burst Bank Switching (RWBS) 短读突发和短写突发银行开关(RWBS)
• Simulation Results

15.4.10 Revisiting the 8-Bank and 16-Bank Issue with DRAMSim

15.4.11 8 Bank vs. 16 Banks — Relaxed tFAW and tWTR

15.4.12 Effect of Transaction Ordering on Latency Distribution

15.5 A Latency-Oriented Study

15.5.1 Experimental Framework

15.5.2 Simulation Input

15.5.3 Limit Study : Latency Bandwidth Characteristics

15.5.4 Latency

15.6 Concluding Remarks

part3 disk

第16章 Overview of Disks

16.1 History of Disk Drives

16.1.1 Evolution of Drives

16.1.2 Areal Density Growth Trend 亚真实密度增长趋势

16.2 Principles of Hard Disk Drives 硬盘驱动器的工作原理

16.2.1 Principles of Rotating Storage Devices 旋转存储装置的原理

16.2.2 Magnetic Rotating Storage Device—Hard Disk Drive 磁性旋转存储装置——硬盘驱动器

16.3 Classifications of Disk Drives

16.3.1 Form Factor外形因素

16.3.2 Application

16.3.3 Interface

16.4 Disk Performance Overview

16.4.1 Disk Performance Metrics

• Response Time and Service Time
• Throughput
• Response Time vs. Throughput

16.4.2 Workload Factors Affecting Performance

16.4.3 Video Application Performance

16.5 Future Directions in Disks 磁盘的5个未来方向

第17章 The Physical Layer

This chapter presents a high-level overview of magnetic recording and the major physical components of a disk drive.

17.1 Magnetic Recording

17.1.1 Ferromagnetism 铁磁性

17.1.2 Magnetic Fields 磁场

17.1.3 Hysteresis Loop 滞后循环

17.1.4 Writing

17.1.5 Reading

17.2 Mechanical and Magnetic Components 机械和磁性组件

17.2.1 Disks

• Substrates 基板
• Magnetic Layer 磁层
• Disk Structure

17.2.2 Spindle Motor 主轴电机

• Bearings 轴承

17.2.3 Heads 磁头？

• Write Heads
• Read Heads
• Read/Write Heads

17.2.4 Slider and Head-Gimbal Assembly 滑块和磁头起动臂总成

17.2.5 Head-Stack Assembly and Actuator 头堆栈组件和执行机构

17.2.6 Multiple Platters 多个平台

17.2.7 Start/Stop

• Contact Start/Stop
• Load/Unload

17.2.8 Magnetic Disk Recording Integration 磁盘记录系统集成

• Tracks per Inch 每英寸道数
• Bits per Inch 每英寸比特数
• Tribology 摩擦学

17.2.9 Head-Disk Assembly 头部磁盘组件

17.3 Electronics 电子产品

17.3.1 Controller

17.3.2 Memory

17.3.3 Recording Channel

• Write Channe
• Read Channe

17.3.4 Motor Controls

第18章 The Data Layer

18.1 Disk Blocks and Sectors 磁盘块和分区

18.1.1 Fixed-Size Blocks

18.1.2 Variable Size Blocks

18.1.3 Sectors

• Anatomy of a Sector
• Sector Size

18.2 Tracks and Cylinders 轨道和柱

• Cylinders 柱

18.3 Address Mapping

18.3.1 Internal Addressing

18.3.2 External Addressing

18.3.3 Logical Address to Physical Location Mapping

• Cylinder Mode 同位标磁道组方式
• Serpentine Format 蛇形的格式
• Skewing 时（间）滞（后），（两个相关信号间的）相位差

18.4 Zoned-Bit Recording 分区位记录

18.4.1 Handling ZBR

Variable Rotational Speed 可变转速

Variable Data Rate可变数据速率

18.5 Servo 伺服器

18.5.1 Dedicated Servo 专用伺服系统

18.5.2 Embedded Servo 嵌入伺服系统

18.5.3 Servo ID (Identifi cation) and Seek 伺服标识和查找

18.5.4 Servo Burst and Track Following 伺服突然和跟踪

18.5.5 Anatomy of a Servo 解剖伺服

18.5.6 ZBR and Embedded Servo zbr和嵌入式伺服器

18.6 Sector ID and No-ID Formatting

18.7 Capacity

18.8 Data Rate

18.9 Defect Management 缺陷管理

18.9.1 Relocation Schemes 迁移方案

• Sector Slipping
• Sector Sparing

18.9.2 Types of Defects 缺陷类型

• Primary Defects 主要缺陷
• Grown Defects 诱发的缺陷

18.9.3 Error Recovery Procedure 错误恢复程序

第19章 Performance Issues and Design Trade-Offs

19.1 Anatomy of an I/O 解剖IO

19.1.1 Adding It All Up

• Random Access
• Sequential Access

19.2 Some Basic Principles

19.2.1 Effect of User Track Capacity

• Media Data Rate
• Number of Track/Cylinder Switches
• Constraint on rpm

19.2.2 Effect of Cylinder Capacity

19.2.3 Effect of Track Density

• Travel Time
• Settle Time 稳定时间

19.2.4 Effect of Number of Heads 磁头数目的影响

• Cylinder Size 柱的尺寸

19.3 BPI vs. TPI

19.4 Effect of Drive Capacity

19.4.1 Space Usage Efficiency

19.4.2 Performance Implication

• Large Files
• Small File

19.5 Concentric Tracks vs. Spiral Track 同心轨道和螺旋轨道

19.5.1 Optical Disks 光盘

19.6 Average Seek 平均搜索次数

19.6.1 Disks without ZBR

19.6.2 Disks with ZBR

第20章 Drive Interface

20.1 Overview of Interfaces

20.1.1 Components of an Interface

20.1.2 Desirable Characteristics of Interface 接口的理想特性

20.2 ATA

20.3 Serial ATA

20.4 SCSI

20.5 Serial SCSI

20.6 Fibre Channel 光纤通道

20.7 Cost, Performance, and Reliability

第21章 Operational Performance Improvement

21.1 Latency Reduction Techniques 延迟减少技术

21.1.1 Dual Actuator 双执行机构

21.1.2 Multiple Copies 多份副本

21.1.3 Zero Latency Access 0延迟访问

21.2 Command Queueing and Scheduling 命令排队和调度

21.2.1 Seek-Time-Based Scheduling 基于搜索时间的调度

21.2.2 Total-Access-Time-Based Scheduling 基于总访问时间的调度

• Estimating Access Time 预估访问时间
• Simplifi ed Sorting Methods 简单排序
• Performance Comparison 性能比较
• Practical Issues of SATF SATF的实际问题

21.2.3 Sequential Access Scheduling 顺序访问的调度

21.3 Reorganizing Data on the Disk 磁盘数据的重新组织

21.3.1 Defragmentation 碎片整理

21.3.2 Frequently Accessed Files 经常被访问的文件

21.3.3 Co-Locating Access Clusters 联合定位访问集群

21.3.4 ALIS

• Heat Clustering 热集群
• Run Clustering 运行集群
• Cluster Selection During Service Time 服务时间期间的集群选择

21.4 Handling Writes

21.4.1 Log-Structured Write

21.4.2 Disk Buffering of Writes

21.5 Data Compression

第22章 Cache层

22.1 Disk Cache

22.1.1 Why Disk Cache Works

22.1.2 Cache Automation

22.1.3 Read Cache, Write Cache

• Read Caching
• Write Caching
• Read Caching in the Presence of a Write Cache

22.2 Cache Organizations

22.2.1 Desirable Features of Cache Organization cache的理想功能

22.2.2 Fixed Segmentation 固定分段

22.2.3 Circular Buffer

22.2.4 Virtual Memory Organization 虚拟内存组织

• Logical Segment
• LBA Mapping
• Hashing
• Page Table
• Cache Lookup Procedure
• Attributes of Architecture

22.3 Caching Algorithms

22.3.1 Perspective of Prefetch 预取数据的角度

22.3.2 Lookahead Prefetch 正在查找的预取

22.3.3 Look-behind Prefetch 查找预取

22.3.4 Zero Latency Prefetch 0延迟预取

22.3.5 ERP During Prefetch 预取期间的ERP

22.3.6 Handling of Sequential Access 顺序访问的处理

22.3.7 Replacement Policies 替换策略

第23章 Performance Testing

23.1 Test and Measurement

23.1.1 Test Initiator

• Methods of Test Generation

23.1.2 Monitoring and Measuring

23.1.3 The Test Drive

23.2 Basic Tests

23.2.1 Media Data Rate

23.2.2 Disk Buffer Data Rate

23.2.3 Sequential Performance

23.2.4 Random Performance

23.2.5 Command Reordering Performance

23.3 Benchmark Tests

23.3.1 Guidelines for Benchmarking

• Test System
• Ideal Setup
• Multiple Runs

23.4 Drive Parameters Tests

23.4.1 Geometry and More

• A Test Method

23.4.2 Seek Time

第24章 Storage Subsystems

24.1 Data Striping 数据条带

24.2 Data Mirroring 数据镜像

24.2.1 Basic Mirroring 基本镜像

24.2.2 Chained Decluster Mirroring 链条暗镜像？

24.2.3 Interleaved Decluster Mirroring 交错暗镜像

24.2.4 Mirroring Performance Comparison 性能比较

• Normal Mode
• Degraded Mode 降级模式
• Rebuild Mode 重建模式

24.2.5 Mirroring Reliability Comparison 可靠性比较

• Basic Mirroring
• Chained Decluster Mirroring
• Interleaved Decluster Mirroring

24.3 RAID

24.3.1 RAID Levels

• RAID-0
• RAID-1
• RAID-2
• RAID-3
• RAID-4
• RAID-5
• RAID-6

24.3.2 RAID Performance

• Normal Mode Performance
• Degraded Mode and Rebuild Mode Performance

24.3.3 RAID Reliability

24.3.4 Sparing 稀疏性

• Global Sparing 全局共享
• Distributed Sparing 分布式空间共享

24.3.5 RAID Controller

24.3.6 Advanced RAIDs

• Declustered RAID 分散集群RAID
• Hierarchical RAID 层次结构RAID

24.4 SAN

24.5 NAS

24.6 iSCSI

第25章 Advanced Topics

25.1 Perpendicular Recording 垂直度记录

25.1.1 Write Process, Write Head, and Media 写入过程，写入头，写入媒体

25.1.2 Read Process and Read Head 读过程和读头

25.2 Patterned Media 图案媒体

25.2.1 Fully Patterned Media 全图案媒体

25.2.2 Discrete Track Media 离散轨道介质

25.3 Thermally Assisted Recording 热辅助记录

25.4 Dual Stage Actuator 双执行机构

25.4.1 Microactuators 微执行结构

25.5 Adaptive Formatting 自适应格式化

25.6 Hybrid Disk Drive 混合磁盘驱动器

25.6.1 Benefits

25.6.2 Architecture

25.6.3 Proposed Interface

25.7 Object-Based Storage

25.7.1 Object Storage Main Concept

25.7.2 Object Storage Benefits

• Performance
• Sector Size
• Security
• Sharing
• Scalability
• Automation of Storage Management 存储管理的自动化

第26章 Case Study

26.1 The Mechanical Components 机械器件

26.2 Electronics 电子产品

26.3 Data Layout 数据布局

26.3.1 Data Rate

26.4 Interface

26.5 Cache

26.6 Performance Testing

26.6.1 Sequential Access

26.6.2 Random Access

第27章 Cross-Cutting Issues

27.1 Anecdotes, Revisited 轶事，已修订

27.1.1 Anecdote I: Systemic Behaviors Exist 系统行为的存在

27.1.2 Anecdote II: The DLL in DDR SDRAM DLL SDRAM中的DLL

27.1.3 Anecdote III: A Catch-22 in the Search for Bandwidth 在带宽搜索中的陷阱22

27.1.4 Anecdote IV: Proposals to Exploit Variability in Cell Leakage 利用cell泄漏变异性的建议

27.2 Perspective 看法

第28章 Analysis of Cost and Performance 成本和性能的分析

28.1 Combining Cost and Performance 结合成本和性能

28.2 Pareto Optimality 帕累托最优性

28.2.1 The Pareto-Optimal Set: An Equivalence Class 帕累托最优集：一个等价类

28.2.2 Stanley’s Observation 斯坦利的观察结果

28.3 Taking Sampled Averages Correctly 正确抽取样本平均值

28.3.1 Sampling Over Time 随时间变化的取样

28.3.2 Sampling Over Distance 超距离采样

28.3.3 Sampling Over Fuel Consumption 燃油消耗取样

28.3.4 The Moral of the Story 这个故事的寓意

28.4 Metrics for Computer Performance 衡量计算机性能的指标

28.4.1 Performance and the Use of Means 性能和均值的使用

28.4.2 Problems with Normalization 在规范化时存在的问题

• Example 1: Average Normalized by Reference Times 按参考时间标准化的平均标准化
• Example 2: Average Normalized by Number of Operations 按操作数标准化的平均值
• Example 3: Average Normalized by Both Times and Operations 按时间和操作同时标准化的平均值

28.4.3 The Meaning of Performance 性能的意义

• Perspective: Performance Is Time Saved 性能节约了时间
• The Bottom Line

28.5 Analytical Modeling and theMiss-Rate Function

28.5.1 Analytical Modeling 分析建模

28.5.2 The Miss-Rate Function 漏率功能

第29章 Power and Leakage 能源和泄露设备

29.1 Sources of Leakage in CMOS Devices CMOS设备中的泄漏来源

29.2 A Closer Look at Subthreshold Leakage 更仔细地观察阈值以下的泄漏

29.3 CACTI and Energy/Power Breakdown of Pipelined Nanometer Caches 管道纳米缓存的 和能量/功率故障

29.3.1 Leakage in SRAM Cells SRAM cell中的泄露

29.3.2 Pipelined Caches 管道cache

29.3.3 Modeling 建模

29.3.4 Dynamic and Static Power 动态和静态功率

29.3.5 Detailed Power Breakdown 详细的电源故障

第30章 Memory Errors and Error Correction

30.1 Types and Causes of Failures 故障类型和原因

30.1.1 Alpha Particles 阿尔法颗粒

30.1.2 Primary Cosmic Rays and Terrestrial Neutrons 主要的宇宙射线和陆地中子

30.1.3 Soft Error Mechanism 软性错误机制

30.1.4 Single-Bit and Multi-Bit Failures 单位和多位故障

30.2 Soft Error Rates and Trends 软错误率和发展趋势

30.3 Error Detection and Correction 错误检测和纠正

30.3.1 Parity 平价

30.3.2 Single-Bit Error Correction (SEC ECC) 单位纠错

• Single-Bit Error Detection for SEC ECC SEC ECC的单位纠错
• Two-Bit Error in SEC ECC Code Word 两bit纠错

30.3.3 Single-Bit Error Correction, Double-Bit Error Detection (SECDED ECC) 单位纠错，双位误差检测(SECDEDECC)

30.3.4 Multi-Bit Error Detection and Correction: Bossen’s b-Adjacent Algorithm 多位误差检测与校正：博森的b-相邻算法

30.3.5 Bit Steering and Chipkill 位转向和芯片机

30.3.6 Chipkill with x8 DRAM Devices 具有x8DRAM设备的芯片技术

30.3.7 Memory Scrubbing 内存清理

30.3.8 Bullet Proofing the Memory System 内存系统符号证明

30.4 Reliability of Non-DRAM Systems 非DRAM系统的可靠性

30.4.1 SRAM

30.4.2 Flash

30.4.3 MRAM

30.5 Space Shuttle Memory System 航天飞机存储系统

第31章 Virtual Memory

31.1 A Virtual Memory Primer 虚拟内存引言？

31.1.1 Address Spaces and the Main Memory Cache 地址空间和贮存cache

31.1.2 Address Mapping and the Page Table 地址映射和页表

31.1.3 Hierarchical Page Tables 层次结构页表(vpn 索引)

有两种查找方法，Top-Down Traversal 和 Bottom-Up Traversal

• Top-Down Traversal 自上而上遍历
• Bottom-Up Traversal

31.1.4 Inverted Page Tables 反转页表

31.1.5 Comparison: Inverted vs. Hierarchical 倒置与层次结构

31.1.6 Translation Lookaside Buffers, Revisited 翻译查找备用缓冲区，已重置

31.1.7 Perspective: Segmented Addressing Solves the Synonym Problem 观点：分段寻址解决了同义词的问题

• Segmented Architectures 分段式体系结构
• The “Virtue” of Segmentation 分段的美德
• Disjunct Page Table 分离的页表

31.1.8 Perspective: A Taxonomy of Address Space Organizations 观点：地址空间组织的分类法

31.2 Implementing Virtual Memory 虚拟内存的实现

31.2.1 The Basic In-Order Pipe 基本的有序管道

31.2.2 Precise Interrupts in Pipelined Computers 管道式计算机的精确中断

• System-Level Instruction-Set Extensions 系统级指令扩展
• Control Registers, Generally 通用控制寄存器
• Processor Status Register 处理机状态寄存器
• Concrete Example: RiSC-16 TLB and Page Table Organization 具体示例：RiSC-16TLB和页表组织结构

DRAM书籍笔记 - 目录整理相关推荐

1. C++书籍笔记目录汇总【目前1本读书笔记（持续更新中……）】

   C++书籍笔记汇总 C++Primer Plus (第六版)阅读笔记 + 源码分析[目录汇总]

2. 【Unity】Unity学习笔记目录整理

   概述及周边 [Unity]Unity 基本介绍 [Unity]Unity 相关知识分类 [Unity]Unity 特殊文件夹[未完成] [Unity]Unity 常用插件 基础知识 [Unity]Un ...

3. Dram学习笔记(2) 读《终极内存技术指南》笔记 + 纠正一些流传很广的文章错误

   文章目录 0. 引言 1. Dram 名词解释 2. 一些流程步骤的梳理 2.1 内存结构 2.2 一次burst的实现 2.3 一次mask burst的实现 3. 不懂的地方 3.1 数据在内存里 ...

4. 一份详细的“入坑Phd指南”---教你如何做笔记、整理参考书目、管理时间、如何写作、对自己和导师合理预期...

   点击上方,选择星标或置顶,每天给你送干货! 阅读大概需要5分钟 pick小博主,每天进步一丢丢 [导读]今天给大家强烈推荐一份详细的读博指南,本指南教你如何做笔记.整理参考书目.管理时间.如何写作.对 ...

5. 前端面试知识点目录整理

   前端面试知识点目录整理 基本功考察 1.关于Html 1.html语义化标签的理解.结构化的理解:能否写出简洁的html结构:SEO优化. 2.h5中新增的属性,如自定义属性data.类名classN ...

6. 【笔记目录】南邮(通达)计算机专业基础

   计算机专业基础 数据结构 数据库系统设计 计算机网络 网络信息安全 嵌入式系统与开发 微型计算机原理与接口技术 操作系统 计算机组成原理 Java Linux 数据结构 数据结构的笔记目录:[恋上数据 ...

7. Swing学习笔记目录

   本篇文章总结一下全部的Swing笔记,算得上是一个大纲了吧. 本篇笔记目录全部摘抄自网上系列教程,由本人整合而来,也算是记录一下自己的学习经历.要转载的请注明出处,谢谢. Swing学习笔记 1. S ...

8. 【从线性回归到 卷积神经网络CNN 循环神经网络RNN Pytorch 学习笔记 目录整合 源码解读 B站刘二大人 绪论（0/10）】

   深度学习 Pytorch 学习笔记 目录整合 数学推导与源码详解 B站刘二大人 目录传送门: 线性模型 Linear-Model 数学原理分析以及源码详解 深度学习 Pytorch笔记 B站刘二大人( ...

9. [Vue]学习笔记目录 【Vue2与Vue3完结】 (尚硅谷Vue2.0+Vue3.0全套教程丨vuejs从入门到精通)

   文章目录 前言 遇见的问题及其解决方案 之前笔记 Vue2 Vue3 前言 本笔记根据如下笔记和视频进行整理 老师的课件笔记,不含视频 https://www.aliyundrive.com/s/B8 ...

最新文章

1. C#基础-类成员（Day7）
2. EigenUbuntu下的配置
3. django创建一个管理员用户
4. Spring bean注入之注解注入-- @Autowired原理
5. 设计模式：装饰模式（Decorator）
6. 10.32/10.33 rsync通过服务同步 10.34 linux系统日志 screen工具
7. Spark-Streaming基础
8. C/C++ _wcslwr_s 函数 – unicode 字符串大写转小写 - C语言零基础入门教程
9. python另一个程序正在使用此文件_另一个程序正在使用此文件，进程无法访问
10. flutter ios上踩的一个坑
11. HP-UX 中配置Trusted System
12. MyEclipse中防止代码格式化时出现换行
13. JAVAWeb项目 微型商城项目-------(一)项目描述
14. php 5的手册,本手册中所涉及的 PHP 版本 - PHP 5 中文文档
15. Bootstrap-CSS全样式
16. windows创建服务删除服务
17. 排错万能金钥匙之Linux系统应用
18. 微信没有回车键怎么换行_微信打字怎么换行
19. 计算机管理老是自动打开,win10系统打开设备管理器后一直自动刷新的设置方案...
20. 我的算法基础实验代码-上篇

热门文章

1. android crash 追踪方式
2. 不兼容结构的协调——适配器模式（四）
3. 《机器人SLAM导航核心技术与实战》第1季：第4章_机器人传感器
4. 华为18级工程师三年心血终成趣谈网络协议文档（附讲解）
5. kedacom摄像头怎么预置_(word)科达KEDACOM TrueVixon100视频会议摄像头.doc
6. 程序猿的困惑之为什么学了很多都记不住？
7. 这些年一直记不住的 Java I/O
8. jQuery农历黄历日期表
9. android系统adb命令
10. 编码（RZ NRZ NRZI）