module float2fixed_pipeline(input [31:0] float_in,input enable,input clk,input rst,output reg [31:0] fixed_out,output reg valid);reg [30:0] M_copy;reg [4:0] shift_value;reg shift_direction;        //0, shift left; 1, shift rightreg sign;                   //符号位reg valid_count;// Pipeline level 1always @ (posedge clk or posedge rst) begin //synchronous enable and asynchronous resetif(rst) beginshift_value <= 5'd0;shift_direction <= 1'b0;sign <= 1'b0;M_copy <= 31'd0;endelse if(enable) beginsign <= float_in[31];M_copy <= {8'd1,float_in[22:0]};if(float_in[30:23] <= 8'd127) begin    //E <= 127,shfit {1'b1,M} right to get I(指数) and F（小数）shift_direction <= 1'b1;shift_value <= 8'd127 - float_in[30:23];endelse begin                            //E > 127,shfit {1'b1,M} left to get I and Fshift_direction <= 1'b0;shift_value <= float_in[30:23] - 8'd127;//2^7-1end         endelse begin        //enable = 0, Maintain the previous valueshift_value <= shift_value;shift_direction <= shift_direction;sign <= sign;M_copy <= M_copy;endend// Output logicalways @ (posedge clk or posedge rst) begin //synchronous enable and asynchronous resetif(rst) beginfixed_out <= 32'd0;endelse if(enable) begin if(shift_direction) begin        //E <= 127,shfit {1'b1,M} right to get I and Ffixed_out <= {sign,M_copy >> shift_value};endelse begin                        //E > 127,shfit {1'b1,M} left to get I and Ffixed_out <= {sign,M_copy << shift_value};endendelse begin        //enable = 0, Maintain the previous valuefixed_out <= fixed_out;endend// The valid output logicalways @ (posedge clk or posedge rst) begin    //asynchronous resetif(rst) beginvalid <= 1'b0;valid_count <= 1'd0;endelse if(enable) beginif(valid_count == 1'd1) begin    //Maintain valid as ture unless resetvalid <= 1'b1;valid_count <= valid_count;endelse beginvalid_count <= 1'b1;valid <= 1'b0;endendelse begin        //enable = 0, Maintain the previous valuevalid <= valid;valid_count <= valid_count;endend    endmodule

// Output logicalways @ (posedge clk or posedge rst) begin //synchronous enable and asynchronous resetif(rst) beginfloat_out <= 32'd0;endelse if(enable) beginif(fixed_shift_reg3[22] == 1'b1) beginfloat_out <= {fixed_shift_reg3[23],8'd127 - shift_count3 - 8'd1 + ((shift_direction3) ? 8'd8 : 8'd0),fixed_shift_reg3[21:0],1'd0};endelse if(fixed_shift_reg3[21] == 1'b1) beginfloat_out <= {fixed_shift_reg3[23],8'd127 - shift_count3 - 8'd2 + ((shift_direction3) ? 8'd8 : 8'd0),fixed_shift_reg3[20:0],2'd0};endelse if(fixed_shift_reg3[20] == 1'b1) beginfloat_out <= {fixed_shift_reg3[23],8'd127 - shift_count3 - 8'd3 + ((shift_direction3) ? 8'd8 : 8'd0),fixed_shift_reg3[19:0],3'd0};endelse begin    //The fixed-point input is zero, -0 will be cast to 0 too.float_out <= {1'b0,8'd127,23'd0};end        endelse begin        //enable = 0, Maintain the previous valuefloat_out <= float_out;endend