int main(void)
{volatile uint32_t cnt = 0;Clock_Init();Port_Init();Clock_Out_Bus();while(1){cnt ++;}return 0;
}

/*** 配置MCU时钟, 使SYS_CLK=80MHz, BUS_CLK=40MHz, FLASH_CLK=20MHz, 用外部晶振f_osc=8MHz* SPLL_CLK=160MHz, VCO_CLK=320MHz* @note* 计算公式:* BUS_CLK=SYS_CLK / DIVBUS* SYS_CLK=SPLL_CLK / DIVCORE* SPLL_CLK=(VCO_CLK) / 2* VCO_CLK=SPLL_SOURCE / (PREDIV + 1) x (MULT + 16)* 选择外部晶振作为SPLL_SOURCE, SPLL_SOURCE=8MHz*/
void Clock_Init(void)
{// 以下初始化顺序不可改变
Clock_SOSC_Init_8M(); // SOSC&SPLL_SOURCE初始化为输出8M
Clock_SPLL_Init_160M(); // SPLL&SCG初始化为输出160M
Clock_RUNMode_SYS_Init_80M(); // sys clock = 80M, bus clock = 40M, flash = 20M

}void Clock_ConfigureOut(SIM_CLKOUTSEL_Type clkoutsel)
{if(clkoutsel <= RTC_CLK){SIM->CHIPCTL &= ~SIM_CHIPCTL_CLKOUTEN_MASK; // disable CLKOUTSIM->CHIPCTL &= ~SIM_CHIPCTL_CLKOUTSEL_MASK; // clear CLKOUT
SIM->CHIPCTL |= SIM_CHIPCTL_CLKOUTSEL(clkoutsel); // select CLKOUT source = clkoutsel
SIM->CHIPCTL |= SIM_CHIPCTL_CLKOUTEN_MASK; // enable CLKOUT
    }
}/*** CLKOUT pin输出Bus CLK*/
void Clock_Out_Bus(void)
{Clock_ConfigureOut(BUS_CLK);
}/*** 配置SOSC_CLK=8M* @output SOSCDIV1_CLK* @output SOSCDIV2_CLK* @note* 外部晶振8M* 计算公式* SOSCDIV1_CLK=SOSC_CLK / SOSCDIV1* SOSCDIV2_CLK=SOSC_CLK / SOSCDIV2*/
void Clock_SOSC_Init_8M(void)
{// Frequency division for SOSCDIV1_CLK, SOSCDIV2_CLKSCG->SOSCDIV=SCG_SOSCDIV_SOSCDIV1(1) // SOSCDIV1=1 : Divide by 1| SCG_SOSCDIV_SOSCDIV2(1);   // SOSCDIV2=1 : Divide by 1
SCG->SOSCCFG=SCG_SOSCCFG_RANGE(0b11) // RANGE=3: 8-40 MHz SOSC// RANGE=3: 8-40 MHz SOSC| SCG_SOSCCFG_HGO(1)    // HGO=0: Configure crystal oscillator for high-gain operation| SCG_SOSCCFG_EREFS(1); // EREFS=1： Internal crystal oscillator of OSC selectedwhile(SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK); /* Ensure SOSCCSR unlocked */SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN(1);      // SOSC Enable
}/*** 配置MCU时钟SPLL_CLK=160M* @require SOSC_CLK = 8M* @output SPLL_CLK*/
void Clock_SPLL_Init_160M(void)
{while(SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK); /* Ensure SPLLCSR unlocked */// 关闭SPLLSCG->SPLLCSR = 0; /* SPLLEN=0: SPLL is disabled (default) */// 配置SCG_SPLLCFG, 使VCO_CLK=320MHz, SPLL_CLK=160MHzSCG->SPLLCFG = SCG_SPLLCFG_PREDIV(0) | SCG_SPLLCFG_MULT(0b11000);SCG->RCCR = SCG_RCCR_SCS(0b0110)  // System Clock Source: System PLL (SPLL_CLK)| SCG_RCCR_DIVCORE(0)   // DIVCORE=0| SCG_RCCR_DIVBUS(1)    // DIVBUS=1| SCG_RCCR_DIVSLOW(1);  // DVISLOW=1// 使能SPLLSCG->SPLLCSR |= SCG_SPLLCSR_SPLLEN_MASK;// Lock SPLLSCG->SPLLCSR |= SCG_SPLLCSR_LK_MASK;
}/*** SYS_CLK = 80M, BUS_CLK = 40M, FLASH_CLK=20M* @require SPLL_CLK=160M* @note SYS_CLK=80MHz,BUS_CLK=40MHz, 使用外部晶振f_osc=8MHz* 前提条件使用SPLL_SOURCE=160M作为system clock* 计算公式:* SYS_CLK=SPLL_CLK / DIVCORE* BUS_CLK=SYS_CLK / DIVBUS* FLASH_CLK=SYS_CLK / DIVSLOW* SPLL_CLK=(VCO_CLK) / 2* VCO_CLK=SPLL_SOURCE / (PREDIV + 1) x (MULT + 16)** =>DIVCORE=1, DIVBUS=1,DIVSLOW=3*/
void Clock_RUNMode_SYS_Init_80M(void)
{// 配置system clock源, DIVCORE, DIVBUS, DIVFLASHSCG->RCCR = SCG_RCCR_SCS(0b0110)// Select System Clock Source: System PLL (SPLL_CLK)| SCG_RCCR_DIVCORE(1)| SCG_RCCR_DIVBUS(1)| SCG_RCCR_DIVSLOW(3);// 检查Clock Status(SCG_CSR) 是否为RCCR配置while(0b0110 != (SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { }
}

#define PORTD14_IDX              14
#define PORTD16_IDX              16#define PORT_CLKOUT_IDX          PORTD14_IDX
#define PORT_LED_GREEN_IDX       PORTD16_IDX/** PTD14 - CLKOUT* PTD16 - GPO for LED*/
void Port_Init(void)
{// Enable clock to PORTDif(PCC->PCCn[PCC_PORTD_INDEX] & PCC_PCCn_PR_MASK){PCC->PCCn[PCC_PORTD_INDEX] |= PCC_PCCn_CGC(1); // Clock enabled to PORTD
    }// Set Port Data DirectionPTD->PDDR |= 1 << PORT_LED_GREEN_IDX; // Port Data Direction: output// set/clear PortD's value
//    PTD->PTSO |= 1 << PORT_LED_GREEN_IDX; // Port Set OutputPTD->PCOR |= 1 << PORT_LED_GREEN_IDX; // Port Clear Output// PTD16 - GPOPORTD->PCR[PORT_LED_GREEN_IDX] = PORT_PCR_MUX(0b0000001); // Port D16: MUX=ALT1, GPIO(to green LED on EVB/PCB)// PTD14 - CLKOUTPORTD->PCR[PORT_CLKOUT_IDX] = PORT_PCR_MUX(0b00000111);  // Port D14: MUX=ALT4, CLKOUT

}

/*** CLKOUT pin输出Bus CLK*/
void Clock_Out_Bus(void)
{Clock_ConfigureOut(0b1001);
}void Clock_ConfigureOut(SIM_CLKOUTSEL_Type clkoutsel)
{if(clkoutsel <= 0b1110){SIM->CHIPCTL &= ~SIM_CHIPCTL_CLKOUTEN_MASK; // disable CLKOUTSIM->CHIPCTL &= ~SIM_CHIPCTL_CLKOUTSEL_MASK; // clear CLKOUT
SIM->CHIPCTL |= SIM_CHIPCTL_CLKOUTSEL(clkoutsel); // select CLKOUT source = clkoutsel
SIM->CHIPCTL |= SIM_CHIPCTL_CLKOUTEN_MASK; // enable CLKOUT
    }
}