Chisel 教程翻译之第一章：概述介绍《Digital Design with Chisel》

1 Introduction
1 入门
This book is an introduction to digital system design using a modern hardware construction language, Chisel [2].
这本书主要介绍了使用一门现代硬件构建语言Chisel进行数字系统设计。

In this book, we focus on a higher abstraction level than usual
in digital design books, to enable you to build more complex, interacting digital systems in a shorter time.
在这本书里，我们比通常的数字设计的书专注了更高的抽象级别，使你能够在较短的时间里设计出更复杂的、互动的数字系统。

This book and Chisel are targeting two groups of developers: (1) hardware designers and (2) software programmers.
本书以及Chisel本身，瞄准两个开发者群体，一个是硬件设计者，另一个是软件程序员。

Hardware designers who are fluid in VHDL or Verilog
and using other languages such as Python, Java, or Tcl to generate hardware can move
to a single hardware construction language where hardware generation is part of the language.
硬件设计者们熟练的使用VHDL或Verilog，并且使用其他语言，如Python、Java或Tcl来生成硬件。
这样的设计者可以迁移到一个单独的硬件构建语言，硬件生成也是这门语言的一部分，不用使用两门或多门语言。

Software programmers may become interested in hardware design, e.g., as
future chips from Intel will include programmable hardware to speed up programs. It is
perfectly fine to use Chisel as your first hardware description language.

软件程序员可能会变得对硬件设计有兴趣，例如，Intel未来的芯片将会包含可编程硬件，以便加速程序。
使用Chisel作为你的第一门硬件描述语言是极好的。
Chisel brings advances in software engineering, such as object-orientated and functional languages, into digital design.
Chisel把软件工程中的优势带入了硬件设计，例如面向对象和函数式编程。

Chisel does not only allow to express hardware at
the register-transfer level but allows you to write hardware generators.
Chisel不仅仅允许你表示RTL,而且允许你写硬件生成器。

Hardware is now commonly described with a hardware description language.
现在，硬件通常是用硬件描述语言（如VHDL）来描述的。

The time of drawing hardware components, even with CAD tools, is over.
手工画硬件组件的时代已经结束了，即使是使用CAD工具来画硬件，也结束了。

Some high-level schematics can give an overview of the system but are not intended to describe the system.
确实，有一些高级别的电路图能够给人一个系统的概览，但是它并不是用来描述这个系统的。

The two most common hardware description languages are Verilog and VHDL.
两门最通用的硬件描述语言是Verilog和VHDL。

Both languages are old, contain many legacies, and have a moving line of what constructs of the language
are synthesizable to hardware.
两门语言都比较老旧，背负了很多历史包袱，而且就语言的哪些概念能够综合成硬件这件事儿而言，是动态的演进的。

Do not get me wrong: VHDL and Verilog are perfectly able to describe a hardware block
that can be synthesized into an ASIC.
不要误解我的意思哦，当然了，VHDL和Verilog都能够完美地描述一个硬件模块，并且综合成ASIC。

For hardware design in Chisel, Verilog serves as an intermediate language for testing and synthesis.
在用Chisel做硬件设计的时候，Verilog扮演了要给中间语言的角色，以便能够测试和综合所设计的电路。

This book is not a general introduction to hardware design and the fundamentals of it.
这本书不是对硬件设计的通用教材。

For an introduction of the basics in digital design, such as how to build a gate out
of CMOS transistors, refer to other digital design books.
对于数字电路设计的基础介绍，例如怎么样用CMOS晶体管来构建一个门电路等，应该参考其他数字电路设计的书籍。

However, this book intends to teach digital design at an abstraction level
that is current practice to describe ASICs or designs targeting FPGAs.
As prerequisites for this book, we assume basic knowledge of Boolean algebra and the binary number system.
然而，这本书是想讲解在抽象层级的数字设计，当前主要用来针对ASIC和基于FPGA的设计。
本书的预备知识，需要你具备布尔代数和二进制数字系统的知识。

------------注解--start--------------------------------------
As the author is more familiar with FPGAs than ASICs as target technology, some design optimizations
shown in this book are targeting FPGA technology
比起ASIC技术，由于作者更熟悉将FPGA作为目标技术，所以书中有些设计优化主要是针对FPGA技术的。
------------注解--end--------------------------------------

Furthermore, some programming experience in any programming language is assumed.
此外，还希望有一些编程经验，无所谓是哪种编程语言。

No knowledge of Verilog or VHDL is needed.
Chisel can be your first programming language to describe digital hardware.
不需要事先学习过Verilog 或 VHDL。
Chisel可以作为你描述硬件的第一门编程语言。

As the build process in the examples is based on sbt and make,
basic knowledge of the command-line interface (CLI, also called terminal or Unix shell) will be helpful.
因为示例程序的构建过程是基于sb和make程序的，所以基本的命令行接口知识经验是有帮助的。

Chisel itself is not a big language. The basic constructs fit on one page and can be learned within a few days.
Chisel本身不是个大型语言。基本概念不到一页，而且在几天内就能学会。

Therefore, this book is not a big book, as well. Chisel is
for sure smaller than VHDL and Verilog, which carry many legacies.
所以本书也就不是一个大部头的书，Chisel是肯定比VHDL和Verilog小，因为这两者有很多历史包袱。

The power of Chisel comes from the embedding of Chisel within Scala, which itself in an expressive language.
Chisel的的能力来源于它是嵌入在Scala中的，而Scala是一门非常有表现力的语言。

Chisel inherits the feature from Scala being “a language that grows on you” [12].
Chisel继承了从Scala而来的特性，是一门让人越来越喜欢的语言。

However, Scala is not the topic of this book. The textbook by Odersky et
al. [12] provides a general introduction to Scala.
但是Scala并不是本书的主题。Odersky的教材提供了对Scala的整体的详细介绍。（《Scala编程》至少第3版）

This book is a tutorial in digital design and the Chisel language;
it is not a Chisel language reference, nor is it a book on complete chip design.
本书是一本关于Chisel和数字逻辑设计的教程；而不是一本Chisel语言规范，也不是一本完整的关于芯片设计的教程。

All code examples shown in this book are extracted from complete programs that have been compiled and tested.
本书的代码示例都是从完整的经过编译和测试过的程序中抽取的。

Therefore, the code shall not contain any syntax errors.
所以，示例代码不会包含任何语法错误。
The code examples are available from the GitHub repository of this book.
示例代码可以从GitHub中本书的仓库中获得。

Besides showing Chisel code, we have also tried to show useful designs and principles of good hardware
description style.
除了展现Chisel代码以外，我们还尝试着展现了一些优良的硬件描述风格的有用的设计示例与设计原则。

This book is optimized for reading on a laptop or tablet (e.g., an iPad).
本书针对于笔记本阅读或平板阅读而进行了优化。

We include links to further reading in the running text, mostly to Wikipedia articles.
本书还包括了进一步阅读的连接，大多数是维基百科的论文。

1.1 Installing Chisel and FPGA Tools
1.1 安装Chisel和FPGA工具链

Chisel is a Scala library, and the easiest way to install Chisel and Scala is with sbt, the Scala build tool.
Chisel是一个Scala程序库，所以，Chisel和Scala最简单的安装方法是用sbt，sbt是Scala程序的构建工具。

Scala itself depends on the installation of Java JDK 1.8.
而Scala自身依赖Java JDK 1.8.

As Oracle has changed the license for Java, it may be easier to install OpenJDK from AdoptOpenJDK.
因为Oracle已经更改了Java的许可证书，所以，跟简单的方法是从AdoptJDK安装OpenJDK。

1.1.1 macOS
1.1.1 macOS上的安装

Install the Java OpenJDK 8 from AdoptOpenJDK.
从AdoptOpenJDK安装Java OpenJDK 8.

On Mac OS X, with the packet manager Homebrew, sbt and git can be installed with:
在Mac OS X上，用包管理器程序Homebrew，可以用如下命令安装sbt和git。

$ brew install sbt git

Install GTKWave and IntelliJ (the community edition).
安装 GTKWave 和 IntelliJ（社区版即可）

When importing a project, select the JDK 1.8 you installed before (not Java 11!)

当导入项目时，记得选择你刚刚安装的JDK 1.8，一定不要用Java 11的JDK。

1.1.2 Linux/Ubuntu
1.1.2 Linux/Ubuntu上的安装

Install Java and useful tools in Ubuntu with:
在Ubuntu上安装Java和有用的工具，请使用如下命令：

$ sudo apt install openjdk-8-jdk git make gtkwave

For Ubuntu, which is based on Debian, programs are usually installed from a Debian
file (.deb).
因为Ubuntu是基于Debian开发的，所以，通常程序软件也是使用Debian文件（.deb）进行安装的。

However, as of the time of this writing, sbt is not available as a ready to
install package. Therefore, the installation process is a little bit more involved:
然而，在本书写作之际，sbt并没有可以使用的安装包。因此，安装过程就稍微有点复杂：

echo "deb https://dl.bintray.com/sbt/debian /" | \
sudo tee -a /etc/apt/sources.list.d/sbt.list
sudo apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 \
--recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823
sudo apt-get update
sudo apt-get install sbt

1.1.3 Windows
1.1.3 Windows上的安装

Install the Java OpenJDK from AdoptOpenJDK.
从AdoptOpenJDK安装 Java OpenJDK

Chisel and Scala can also be installed
and used under Windows. Install GTKWave and IntelliJ (the community edition).
Chisel和Scala在Windows平台上也是可以安装和使用的。安装GTKWave 和 IntelliJ(社区版即可)

When importing a project, select the JDK 1.8 you installed before (not Java 11!) sbt can be
installed with a Windows installer, see: Installing sbt on Windows.
当你导入一个项目是，记得选择你刚刚安装的 JDK 1.8，一定不要用Java 11的JDK。
sbt可以使用Windows安装器，请看连接文章：在windows上安装sbt。

Install a git client.
安装一个git客户端。

1.1.4 FPGA Tools
1.1.4 安装FPGA 工具链
To build hardware for an FPGA, you need a synthesize tool.
为FPGA构建硬件，你需要一个综合工具。

The two major FPGA vendors, Intel{2} and Xilinx,
provide free versions of their tools that cover small to mediumsized FPGAs.
最大的两个FPGA制造商，Intel和Xilinx，提供了自由的工具版本，这些工具覆盖了小型到中型尺寸的FPGA.

Those medium-sized FPGAs are large enough to build multicore RISC
style processors.
这些中型的FPGA已经足够跑多核RISC风格的处理器了。（牛逼）

Intel provides the Quartus Prime Lite Edition and Xilinx the Vivado
Design Suite, WebPACK Edition.
Intel 提供了 Quartus Prime Lite Edition，而Xilinx 提供了 Vivado
Design Suite, WebPACK Edition. （英文pdf有连接网址）

Both tools are available for Windows and Linux, but not for macOS.
两种工具都有Win版和Lin版，但是没有macOS版。

1.2 Hello World
1.2 Hello World程序
Each book on a programming language shall start with a minimal example, called the
Hello World example.
每一本编程书籍都会从一个最小的示例程序开始，也就是Hello World 示例。

Following code is the first approach:
下面代码是第一次靠近Chisel程序设计：

-------注解--start-------------------------------
2former Altera
前身是Altera公司，被Intel收购
-------注解--end-------------------------------

//Chisel source code, you can save these in HelloScala.scala
object HelloScala extends App{
println("Hello Chisel World!")
}

Compiling and executing this short program with sbt
用如下sbt命令编译执行这段程序：

$ sbt run

leads to the expected output of a Hello World program:
这个HelloWorld程序会产生如下输出：
[info] Running HelloScala
Hello Chisel World!

However, is this Chisel? Is this hardware generated to print a string? No,
this is plain Scala code and not a representative Hello World program for a hardware design.
然而，这是Chisel程序么？这会生成一个硬件模块，然后打印一个字符串么？不会的，
这是个简单的Scala代码，并不是硬件设计中有代表性的HelloWorld程序。

1.3 Chisel Hello World
1.3 Chisel 的 Hello World程序

What is then the equivalent of a Hello World program for a hardware design?
一个硬件设计领域中相应的Hello World程序是什么样子呢？

The minimal useful and visible design? A blinking LED is the hardware (or even embedded software) version of Hello World.
最小的、有用的、能够看得见的？一个闪烁的LED 是硬件版（也是嵌入式版软件）的HelloWorld程序。

If a LED blinks, we are ready to solve bigger problems!
如果我们能够设计让LED闪烁，那么我们就预备好了解决更大的问题。

Listing 1.1 shows a blinking LED, described in Chisel.
列表1.1展示了要给闪烁的LED，使用Chisel描述的。

It is not important that you understand the details of this code example.
暂时你是否能够理解这段示例程序，并不重要。

We will cover those in the following chapters.
我们会在接下来的章节中给出解释。

Just note that the circuit is usually clocked with a high frequency, e.g., 50 MHz,
and we need a counter to derive timing in the Hz range to achieve a visible blinking.
只需要注意，这个电路通常是一个高频时钟驱动的，比如50MHz，并且我们需要要给计时器帮助降频，以便获得一个肉眼可见的闪烁。

//-----Listing 1.1--start----------------------
class Hello extends Module {
   val io = IO(new Bundle {
       val led = Output(UInt(1.W))
   })
   val CNT_MAX = (50000000 / 2 - 1).U;
   val cntReg = RegInit(0.U(32.W))
   val blkReg = RegInit(0.U(1.W))
   cntReg := cntReg + 1.U
   when(cntReg === CNT_MAX) {
       cntReg := 0.U
       blkReg := ~blkReg
   }
   io.led := blkReg
}
//-----Listing 1.1--end----------------------

Listing 1.1: A hardware Hello World in Chisel

In the above example, we count from 0 up to 25000000-1 and then toggle the blinking signal (blkReg := ~blkReg)
and restart the counter (cntReg := 0.U).
上面的这个例子中，我们从0计数到25000000-1 ，然后切换闪烁信号（blkReg := ~blkReg）,并且重启计数器。（cntReg := 0）.

That hardware then blinks the LED at 1 Hz.
这个电路会以每秒钟一次的频率让LED闪烁。

1.4 An IDE for Chisel
1.4 选择要给IDE来开发Chisel吧
This book makes no assumptions about your programming environment or editor you use.
本书并没有预设你使用的编程环境或编辑器。

Learning the basics should be easy with just using sbt at the command line and an
editor of your choice.
学习基础知识时，仅仅在命令行中使用sbt并且使用一个文本编辑器，是最简单的方法。

In the tradition of other books, all commands that you shall type in a shell/terminal/CLI
are preceded by a $ character, which you shall not type in.
其他教材的传统做法，所有那些你应该输入的命令都会以一个$符号开头，当然这个$符号是不需要输入的。

As an example, here is the Unix ls command, which lists files in the current folder:
例如Unix系统中的ls命令，它会罗列显式出当前文件夹的文件。
$ ls

That said, an integrated development environment (IDE), where a compiler is running
in the background, can speed up coding.
也就是说，用IDE时，编译器是在背后运行的，这样可以提高开发速度。

As Chisel is a Scala library, all IDEs that support Scala are also good IDEs for Chisel.
因为Chisel是一个Scala库，所有支持Scala开发的IDE可以很适合用来开发Chisel。

It is possible in IntelliJ and Eclipse to generate a project from the sbt project configuration in build.sbt.
一个基于build.sbt配置的Chisel项目，是可以使用IntelliJ和Eclipse生成项目的。

In IntelliJ you can create a new project from existing sources with: File - New -
Project from Existing Sources... and then select the build.sbt file from the project.
比如，在IntelliJ中，你可以基于已存在的代码创建要给新的项目，步骤如下：File - New -
Project from Existing Sources... 并且从项目中选择build.sbt文件即可。

In Eclipse you can create a project via and import that project into Eclipse.
在Eclipse中，你可以使用如下命令创建并导入一个原有项目：

$ sbt eclipse

Visual Studio Code is another option for a Chisel IDE.
visual studio code（VSC）是另一个适合于开发Chisel的IDE软件。

The Scala Metals extension provides Scala support.
在VSC中， Scala Metals extension 提供了对Scala的支持。

On the left bar select Extensions and search for Metals and
install Scala (Metals).
在VSC界面的左上角，单击Extensions按钮，并且输入查找"Metals",会出现Scala(Metals)(此时是1.9.4版本)

To import an sbt based project open the folder with File - Open.
然后导入一个基于sbt创建的项目时，只需要File->Open 它即可。

1.5 Source Access and eBook Features
1.5 源码访问和电子书的特点
This book is open source and hosted at GitHub: chisel-book.
本书是一本敏捷开源书，它的主服务器在GitHub: chisel-book.

All Chisel code examples, shown in this book, are included in the repository.
本书中的所有的Chisel源码示例，都在这个仓库里。

The code compiles with a recent version of Chisel, and many examples also include a test bench.
这些代码用一个最近的编译器进行了编译，而且很多示例中还有测试基台。

We collect larger Chisel examples in the accompanying repository chisel-examples.
我们收集了本书中较大型的Chisel示例代码，他们都被处在了GitHub中的伴随仓库：chisel-examples中。

If you find an error or typo in the book,
a GitHub pull request is the most convenient way to incorporate your improvement.
如果你发现了书中的原理性错误或者排版错误，一个GitHub的 pull request 是吸收你的改进的最便利的方式。

You can also provide feedback or comments for improvements by filing an
issue on GitHub or sending a plain, old school email.
你也可以提供一个反馈或者注释来改进，然后通过填写要给GitHub中的issue，或直接发送一份邮件到学校邮箱里。

This book is freely available as a PDF eBook and in classical printed form. The eBook
version features links to further resources and Wikipedia entries.
可以获得本书的免费PDF版本，而且是经典的排版格式。本书的电子版连接了很多资源和维基百科的入口。

We use Wikipedia entries for background information (e.g., binary number system) that does not directly fit into this book.
我们使用维基百科入口来提供背景信息（例如二进制系统），这些内容不太适合直接堆放入本书中。

We optimized the format of the eBook for reading on a tablet, such as an iPad.
我们优化了本书的排版，使其适合在平板上阅读，例如iPad。（有本事也做一个kindle版本的呀）

1.6 Further Reading
1.6 延伸阅读
Here a list of further reading for digital design and Chisel:
这里罗列对于数字逻辑设计和Chisel的延伸阅读资料，第一个比较重要：
• Digital Design: A Systems Approach, by William J. Dally and R. Curtis Harting,
is a modern textbook on digital design. It is available in two versions: using
Verilog or VHDL as a hardware description language.
The official Chisel documentation and further documents are available online:
• The Chisel home page is the official starting point to download and learn Chisel.
• The Chisel Tutorial provides a ready setup project containing small exercises with
testers and solutions.
• The Chisel Wiki contains a short users guide to Chisel and links to further information.
• The Chisel Testers are in their own repository that contains a Wiki documentation.
• The Generator Bootcamp is a Chisel course focusing on hardware generators, as
a Jupyter notebook
• A Chisel Style Guide by Christopher Celio.
• The chisel-lab contains Chisel exercises for the course “Digital Electronics 2” at
the Technical University of Denmark.

1.7 Exercise
1.7 练习
Each chapter ends with a hands-on exercise.
每一章的结尾都有一个动手练习。

For the introduction exercise, we will use an FPGA board to get one LED blinking.
作为本章的练习，我们将使一个FPGA板子上的LED灯闪烁。

As a first step clone (or fork) the chisel-examples repository from GitHub.
第一步，从GitHub上克隆这个仓库：chisel-examples

The Hello World example is in the folder hello-world, set up as a minimal project.
其中，前面提到的Hello World示例程序在hello-world文件夹中，这是本书中最小的Chisel项目。

You can explore the Chisel code of the blinking LED in src/main/scala/Hello.scala.
你可以探索这个让LED闪烁的Chisel代码，它存储在 src/main/scala/Hello.scala文件中。

Compile the blinking LED with the following steps:
克隆编译这个闪烁的LED项目的步骤如下：

$ git clone https://github.com/schoeberl/chisel-examples.git
$ cd chisel-examples/hello-world/
$ sbt run

After some initial downloading of Chisel components, this will produce the Verilog file Hello.v.
在起初下载一些Chisel组件之后，这个编译过程将会产生要给Verilog文件：Hello.v文件.

Explore this Verilog file.
探索这个Verilog文件。

You will see that it contains two inputs clock and reset and one output io led.
你将发现它包含两个输入，一个是时钟，一个是reset信号，还有一个对led的输出。

When you compare this Verilog file with the Chisel module,
you will notice that the Chisel module does not contain clock or reset.
当你对照这个Verilog文件和Chisel文件时，你会发现Chisel模块并不包括时钟信号或重置信号。

Those signals are implicitly generated, and in most designs,
it is convenient not to need to deal with these low-level details.
这些信号都是隐含生成的，而且在大多数设计中，省略处理这些低层次的细节是非常方便的。

Chisel provides register components, and those are connected automatically to clock and reset (if needed).
Chisel提供寄存器组件，而且如果需要的话，它们会自动连接到时钟和重置信号上。

The next step is to set up an FPGA project file for the synthesize tool, assign the
pins, compile5 the Verilog code, and configure the FPGA with the resulting bitfile.
下一步，为综合工具设置FPGA项目文件，安排管脚，编译Verilog代码，然后配置用生成的比特文件配置FPGA。

We cannot provide the details of these steps. Please consult the manual of your Intel Quartus or Xilinx Vivado tool.
这一步我们不能提供操作的细节。请咨询你的Intel Quartus 或 Xilinx Vivado工具的手册。

However, the examples repository contains some ready
to use Quartus projects in folder quartus for several popular FPGA boards (e.g., DE2-115).
然而，示例仓库中包含了一些就绪了的文件，这是为Quartus项目预备的，它们在quartus文件夹中，适用于好几款流行的FPGA板子（例如DE2-115）.

If the repository contains support for your board, start Quartus, open the project, compile
it by pressing the Play button, and configure the FPGA board with the Programmer
button and one of the LEDs should blink.
如果这个仓库包含了支持你的板子的文件，那么启动Quartus，打开项目，单击Play按钮编译它，
并且用这个Programmer按钮配置FPGA板子，然后其中一个LED会闪烁。

Gratulation! You managed to get your first design in Chisel running in an FPGA!
恭喜你！你已经搞定了泡在FPGA上的第一个Chisel设计。

If the LED is not blinking, check the status of reset.
如果LED没有闪烁，那么请检查重置的状态。

On the DE2-115 configuration, the reset input is connected to SW0.
在DE2-115的配置中，重置输入连接在SW0上。

Now change the blinking frequency to a slower or a faster value and rerun the build process.
现在修改闪烁频率变慢，或者变快，然后重新来一遍这个构建过程。

Blinking frequencies and also blinking patterns communicate different “emotions”.
闪烁频率或闪烁模式表达不同的含义。

E.g., a slow blinking LED signals that everything is ok, a fast blinking LED
比如，LED缓缓的慢闪表示系统的一切都顺利，而快速闪烁的LED表示警报状态，有事情发生。

//--注解-4和5--start---------------------------------
If you at the moment have no FPGA board available, continue to read as we will show you a simulation
version at the end of the exercise.
如果你一时间没有FPGA硬件做练习的话，没问题的，请继续阅读下去，我们会在最后给你一个仿真版的练习作业。
The real process is more elaborated with following steps: synthesizing the logic, performing place and
route, performing timing analysis, and generating a bitfile.
仿真过程过程会更加稍微复杂，具体要经历如下步骤：逻辑综合，执行place和路由，时序分析，生成比特文件

However, for the purpose of this introduction example we simply call it “compile” your code.
虽然如此复杂，对于本章的这个介绍性的示例，我们简单地称这一些列过程为编译你的代码。

//--注解---end----------------------
signals an alarm state.
Explore which frequencies express best those two different emotions.
在实验中感受一下，具体什么样的频率能够最好地表达这两种情绪
As a more challenging extension to the exercise, generate the following blinking pattern:
the LED shall be on for 200 ms every second.
作为这个练习的一个有挑战性的拓展，可以尝试产生如下的闪烁模式：让LED灯每200ms闪烁一次。

For this pattern, you might decouple the change of the LED blinking from the counter reset.
为了产生这个闪烁模式，你可以把LED的闪烁跟计数器的重置分开。

You will need a second constant where you change the state of the blkReg register.
你将需要第二常量，用来改变blkReg寄存器的状态。

What kind of emotion does this pattern produce? Is it alarming or more like a sign-of-live signal?
这个模式将会产生什么情绪呢？它更像是一个警报灯呢，还是更像呼吸灯呢？

If you do not have an FPGA board (yet), you can still run the blinking LED example.
如果暂时还没有搞到FPGA 板子，你仍然可以跑这个LED示例程序。

You will use the Chisel simulation. To avoid a too long simulation time change the clock
frequency in the Chisel code from 50000000 to 50000.
你将会使用Chise的仿真工具。为了避免花太长的仿真时间，把Chisel示例代码中的时钟频率从50000000改为50000.

Execute following instruction to simulate the blinking LED:
执行如下命令来开始LED的闪烁仿真：

$ sbt test

This will execute the tester that runs for one million clock cycles.
这将会启动运行一个1000000Hz时钟的测试器。

The blinking frequency depends on the simulation speed, which depends on the speed of your computer.
闪烁频率依赖于仿真的速度，而仿真速度有依赖你的计算机的CPU速度。

Therefore, you might need to experiment a little bit with the assumed clock frequency
to see the simulated blinking LED.
所以，你应该需要多尝试实验几次，基于你的电脑呈现的时钟频率，找到合适的LED闪烁仿真效果。

下面内容是翻译时加入的，不是原书内容

运行$sbt run后再运行sbt test，Chisel仿真效果如下图，光标会在红色箭头处停留一段时间，然后运行结束。

在hello-world项目文件夹里运行sbt run成功后，会在hello-world文件夹下生成一个verilog语言的hello.v文件，一个FIRRTL文件：hello.fir，以及跟Intel 和Xilinx FPGA相关的文件。

//---hello.v----如下：---------

module Hello(input   clock,input   reset,output  io_led
);reg [31:0] cntReg; // @[Hello.scala 20:23]reg [31:0] _RAND_0;reg  blkReg; // @[Hello.scala 21:23]reg [31:0] _RAND_1;wire [31:0] _T_1; // @[Hello.scala 23:20]wire  _T_2; // @[Hello.scala 24:15]wire  _T_3; // @[Hello.scala 26:15]assign _T_1 = cntReg + 32'h1; // @[Hello.scala 23:20]assign _T_2 = cntReg == 32'h17d783f; // @[Hello.scala 24:15]assign _T_3 = ~ blkReg; // @[Hello.scala 26:15]assign io_led = blkReg; // @[Hello.scala 28:10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INITinteger initvar;
`endif
`ifndef SYNTHESIS
initial begin`ifdef RANDOMIZE`ifdef INIT_RANDOM`INIT_RANDOM`endif`ifndef VERILATOR`ifdef RANDOMIZE_DELAY#`RANDOMIZE_DELAY begin end`else#0.002 begin end`endif`endif`ifdef RANDOMIZE_REG_INIT_RAND_0 = {1{`RANDOM}};cntReg = _RAND_0[31:0];`endif // RANDOMIZE_REG_INIT`ifdef RANDOMIZE_REG_INIT_RAND_1 = {1{`RANDOM}};blkReg = _RAND_1[0:0];`endif // RANDOMIZE_REG_INIT`endif // RANDOMIZE
end // initial
`endif // SYNTHESISalways @(posedge clock) beginif (reset) begincntReg <= 32'h0;end else if (_T_2) begincntReg <= 32'h0;end else begincntReg <= _T_1;endif (reset) beginblkReg <= 1'h0;end else if (_T_2) beginblkReg <= _T_3;endend
endmodule

//--------hello.fir----内容如下：----------------------

;buildInfoPackage: chisel3, version: 3.2.2, scalaVersion: 2.12.10, sbtVersion: 1.3.2
circuit Hello : module Hello : input clock : Clockinput reset : UInt<1>output io : {led : UInt<1>}reg cntReg : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Hello.scala 20:23]reg blkReg : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Hello.scala 21:23]node _T = add(cntReg, UInt<1>("h01")) @[Hello.scala 23:20]node _T_1 = tail(_T, 1) @[Hello.scala 23:20]cntReg <= _T_1 @[Hello.scala 23:10]node _T_2 = eq(cntReg, UInt<25>("h017d783f")) @[Hello.scala 24:15]when _T_2 : @[Hello.scala 24:28]cntReg <= UInt<1>("h00") @[Hello.scala 25:12]node _T_3 = not(blkReg) @[Hello.scala 26:15]blkReg <= _T_3 @[Hello.scala 26:12]skip @[Hello.scala 24:28]io.led <= blkReg @[Hello.scala 28:10]

FIRRTL specification:

https://github.com/freechipsproject/firrtl/blob/master/spec/spec.pdf

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