/****************************************************************

*  文件名称： fpga_load_driver.h

*  文件标识： 定义头文件

*  内容摘要： ZYNQ7000平台FPGA软件加载驱动.

*  其它说明： PS->PL加载，涉及PCAP接口.支持bit和bin格式自适应加载.

*

*  当前版本： V1.00.00

*  作    者： root

*  完成日期： 02/19/2020

****************************************************************/

#ifndef __FPGA_LOAD_H__

#define __FPGA_LOAD_H__

//#define  FPGA_LOAD_DEBUG                 1

/* fpga load return value definitions */

#define FPGA_SUCCESS                    0

#define FPGA_FAIL                       -1

int zynq_load_fs(char *pFilePath);

#endif /* __FPGA_LOAD_H__ */

#define ZYNQ_SYS_CTRL_BASEADDR          0xF8000000

#define ZYNQ_DEV_CFG_APB_BASEADDR       0xF8007000

/* Reflect slcr offsets */

struct slcr_regs {

UINT32 scl; /* 0x0 */

UINT32 slcr_lock; /* 0x4 */

UINT32 slcr_unlock; /* 0x8 */

UINT32 reserved0_1[61];

UINT32 arm_pll_ctrl; /* 0x100 */

UINT32 ddr_pll_ctrl; /* 0x104 */

UINT32 io_pll_ctrl;  /* 0x108 */

UINT32 reserved0_2[5];

UINT32 arm_clk_ctrl; /* 0x120 */

UINT32 ddr_clk_ctrl; /* 0x124 */

UINT32 dci_clk_ctrl; /* 0x128 */

UINT32 aper_clk_ctrl; /* 0x12c */

UINT32 reserved0_3[2];

UINT32 gem0_rclk_ctrl; /* 0x138 */

UINT32 gem1_rclk_ctrl; /* 0x13c */

UINT32 gem0_clk_ctrl; /* 0x140 */

UINT32 gem1_clk_ctrl; /* 0x144 */

UINT32 smc_clk_ctrl;  /* 0x148 */

UINT32 lqspi_clk_ctrl; /* 0x14c */

UINT32 sdio_clk_ctrl; /* 0x150 */

UINT32 uart_clk_ctrl; /* 0x154 */

UINT32 spi_clk_ctrl; /* 0x158 */

UINT32 can_clk_ctrl; /* 0x15c */

UINT32 can_mioclk_ctrl; /* 0x160 */

UINT32 dbg_clk_ctrl; /* 0x164 */

UINT32 pcap_clk_ctrl; /* 0x168 */

UINT32 reserved0_4[1];

UINT32 fpga0_clk_ctrl; /* 0x170 */

UINT32 reserved0_5[3];

UINT32 fpga1_clk_ctrl; /* 0x180 */

UINT32 reserved0_6[3];

UINT32 fpga2_clk_ctrl; /* 0x190 */

UINT32 reserved0_7[3];

UINT32 fpga3_clk_ctrl; /* 0x1a0 */

UINT32 reserved0_8[8];

UINT32 clk_621_true; /* 0x1c4 */

UINT32 reserved1[14];

UINT32 pss_rst_ctrl; /* 0x200 */

UINT32 reserved2[15];

UINT32 fpga_rst_ctrl; /* 0x240 */

UINT32 reserved3[5];

UINT32 reboot_status; /* 0x258 */

UINT32 boot_mode; /* 0x25c */

UINT32 reserved4[116];

UINT32 trust_zone; /* 0x430 */ /* FIXME */

UINT32 reserved5_1[63];

UINT32 pss_idcode; /* 0x530 */

UINT32 reserved5_2[51];

UINT32 ddr_urgent; /* 0x600 */

UINT32 reserved6[6];

UINT32 ddr_urgent_sel; /* 0x61c */

UINT32 reserved7[56];

UINT32 mio_pin[54]; /* 0x700 - 0x7D4 */

UINT32 reserved8[74];

UINT32 lvl_shftr_en; /* 0x900 */

UINT32 reserved9[3];

UINT32 ocm_cfg; /* 0x910 */

};

struct devcfg_regs {

UINT32 ctrl; /* 0x0 */

UINT32 lock; /* 0x4 */

UINT32 cfg; /* 0x8 */

UINT32 int_sts; /* 0xc */

UINT32 int_mask; /* 0x10 */

UINT32 status; /* 0x14 */

UINT32 dma_src_addr; /* 0x18 */

UINT32 dma_dst_addr; /* 0x1c */

UINT32 dma_src_len; /* 0x20 */

UINT32 dma_dst_len; /* 0x24 */

UINT32 rom_shadow; /* 0x28 */

UINT32 reserved1[2];

UINT32 unlock; /* 0x34 */

UINT32 reserved2[18];

UINT32 mctrl; /* 0x80 */

UINT32 reserved3;

UINT32 write_count; /* 0x88 */

UINT32 read_count; /* 0x8c */

};

#define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)

#define slcr_base   ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)

#define vxReadl(addr)        *(volatile UINT32 *)(addr)

#define vxWritel(data, addr)    *(volatile UINT32 *)(addr) = (data)

static int zynq_dma_transfer(UINT32 srcbuf, UINT32 srclen, UINT32 dstbuf, UINT32 dstlen)

{

UINT32 isr_status;

struct timeval start_time, now;

/* Set up the transfer */

vxWritel((UINT32)srcbuf, &devcfg_base->dma_src_addr);

vxWritel(dstbuf, &devcfg_base->dma_dst_addr);

vxWritel(srclen, &devcfg_base->dma_src_len);

vxWritel(dstlen, &devcfg_base->dma_dst_len);

isr_status = vxReadl(&devcfg_base->int_sts);

/* Polling the PCAP_INIT status for Set */

gettimeofday(&start_time, NULL);

while (!(isr_status & DEVCFG_ISR_DMA_DONE))

{

if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {

printf("%s: Error: isr = 0x%08X\n", __func__,

isr_status);

printf("%s: Write count = 0x%08X\n", __func__,

vxReadl(&devcfg_base->write_count));

printf("%s: Read count = 0x%08X\n", __func__,

vxReadl(&devcfg_base->read_count));

return FPGA_FAIL;

}

gettimeofday(&now, NULL);

if (now.tv_sec - start_time.tv_sec > CONFIG_SYS_FPGA_PROG_TIME) {

printf("%s: Timeout wait for DMA to complete\n",

__func__);

return FPGA_FAIL;

}

isr_status = vxReadl(&devcfg_base->int_sts);

}

debug("%s: DMA transfer is done\n", __func__);

/* Clear out the DMA status */

vxWritel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);

return FPGA_SUCCESS;

}

int zynq_load_fs(char *pFilePath)

{

int fd;

int ret;

UINT32 swap, diff;

int filehead, fileend, filelen;

UINT32 *buf_start = NULL;

fd = open(pFilePath, O_RDONLY, 0777);

if (fd < 0)

{

printf("no %s such file\n", pFilePath);

return FPGA_FAIL;

}

filehead = lseek(fd, 0, SEEK_SET);

fileend = lseek(fd, 0, SEEK_END);

lseek(fd, 0, SEEK_SET);

filelen = fileend - filehead;

//dcache_disable();

char *buf = (char *)malloc(filelen);

if(NULL == buf)

{

printf("not enough mem!\n");

return FPGA_FAIL;

}

read(fd, (char *)buf, filelen);

buf_start = check_data((UINT8 *)buf, filelen, &swap);

diff = (UINT32)buf_start - (UINT32)buf;

/* fpga bit file */

if (diff != 0)

{

ret = zynq_load(buf+diff, filelen-diff, BIT_FULL);

}

else  /* fpga bin file */

{

ret = zynq_load(buf, filelen, BIT_FULL);

}

//dcache_enable();

if (ret != FPGA_SUCCESS)

{

printf("fpga load fail!\n");

free(buf);

close(fd);

return FPGA_FAIL;

}

printf("fpga load success!\n");

free(buf);

close(fd);

return FPGA_SUCCESS;

}