win8发布,哪家ARM厂商能提前支持win8 RT版本的?
2012-10月26号,win8发布了。话说ARM厂商只有TI,高通,NVIDIA三家获得MS的合作。且NVDIA据说2月份就出了ARM架构的Win8平板电脑,因此看看NVIDIA的双核芯片和三星的有啥优势?对比如下,不知他们价格如何。三星4212的已经有开发板在卖了。不过不是win8的系统。呵呵。
Tegra 3 Specifications:
CPU | Quad-Core, with 5th battery-saver core |
Max Frequency | Up to 1.7 GHz Single Core /1.6 GHz Quad-Core |
L2 Cache | 1 MB |
L1 Cache (I/D) | (32KB / 32KB) per core |
Memory | |
Frequency | DDR3-L 1500 |
LPDDR2-1066 | |
Memory Size | Up to 2 GB |
GPU | |
Architecture | ULP GeForce |
3D Performance Relative to Tegra 2* | Up to 3x |
Cores | 12 |
3D Stereo | Yes |
Full Programmability | Yes |
OpenGL ES Version | 2 |
OpenVG | 1.1 |
EGL | 1.4 |
Video (1080p) | |
Decode | H.264 (HP @ 40Mbps) |
VC-1 AP | |
MPEG2 | |
MPEG-4 | |
DivX 4/5 | |
XviD HT | |
H.263 | |
Theora | |
VP8 | |
WMV | |
Sorenson Spark | |
Real Video | |
VP6 | |
Encode | H.264 |
MPEG4 | |
H.263 | |
VP8 | |
Video Teleconference (VTC) | H.264 |
MPEG4 | |
H.263 | |
VP8 | |
Audio | |
Decode | AAC-LC |
AAC+ | |
eAAC+ | |
MP3 | |
MP3 VBR | |
WAV/PCM | |
AMR-NB | |
AMR-WB | |
BSAC | |
MPEG-2 Audio | |
Vorbis | |
WMA 9 | |
WMA Lossless | |
WMA Pro | |
G.729a * | |
G.711 * | |
QCELP * | |
EVRC * | |
* Through third party | |
Encode | AAC LC |
AAC+ | |
eAAC+ | |
PCM/WAV | |
AMR-NB | |
AMR-WB | |
Imaging | |
Primary Camera | 32 MP |
Secondary Camera | 5 MP |
Mpixel/s | 300 |
Digital Zoom | Up to 16x |
JPEG Decoding/Encoding | 80MP/sec |
Still Image Stabilitization | Yes |
Video Stabilization | Yes |
Features | Auto Exposure |
Auto White Balance | |
Auto Focus | |
Lens Shading 9th order | |
De-Mosaic | |
Sharpening | |
Programmable De-Noise | |
MIPI CSI | Yes |
Display | |
Display Controllers | 2 simultaneous |
HDMI | (1920x1080) |
LCD | 2048x1536 |
CRT | 1920x1200 |
MIPI DSI | Yes |
Package | |
Package | 14x14 BGA |
24.5x24.5 BGA | |
Process | 40 nm |
三星芯片:
Features of Exynos 4212
The features of Exynos 4212 are:
ARM Cortex-A9 based Quad CPU Subsystem with NEON
32/32 KB I/D Cache, 1 MB L2 Cache
Operating frequency up to 800 MHz at 0.9 V, 1 GHz at 1.0 V, and 1.5 GHz at TBD V
128-bit/64-bit Multi-layer bus architecture
Core-D domain for ARM Cortex-A9 Quadl, CoreSight, and external memory interface
Operating frequency up to 200 MHz at 1.0 V
Global D- domain mainly for multimedia components and external storage interfaces
Operating frequency up to 100 MHz at 1.0 V
Core-P, Global-P domain mainly for other system component, such as system peripherals, peripheral DMAs, connectivity IPs and Audio interfaces.
Operating frequency up to 100 MHz at 1.0 V
Audio domain for low power audio play
Advanced power management for mobile applications
64 KB ROM for secure booting and 256 KB RAM for security function
8-bit ITU 601/656 Camera Interface supports horizontal size up to 4224 pixels for scaled and 8192 pixels for un-scaled resolution
Multi Format Codec provides encoding and decoding of MPEG-4/H.263/H.264 up to 1080p@30 fps and decoding of MPEG-2/VC1/Xvid video up to 1080p@30fps
Image Signal Processing subsystem
JPEG encoder supports various format.
3D Graphics Acceleration with scalable Multicore GPU.
2D Graphics Acceleration support.
1/2/4/ 8bpp Palletized or 8/16/24bpp Non-Palletized Color TFT recommend up to SXGA resolution
HDMI interface support for NTSC and PAL mode with image enhancer
MIPI-DSI and MIPI-CSI interface support
One AC-97 audio codec interface and 3-channel PCM serial audio interface
Three 24-bit I2S interface support
One TX only S/PDIF interface support for digital audio
Eight I2C interface support
Three SPI support
Four UART supports three Mbps ports for Bluetooth 2.0
On-chip USB 2.0 Device supports high-speed (480 Mbps, on-chip transceiver)
On-chip USB 2.0 Host support
Two on-chip USB HSIC
Four SD/ SDIO/ HS-MMC interface support samsung / david.pang at 09:44,2011.12.06
SAMSUNG
Samsung Confidential
Exynos 4212_UM 1 Product Overview
1-4
Preliminary product information describes products that are in development, for which full characterization data and
associated errata are not yet available. Specifications and information herein are subject to change without notice.
32-channel DMA controller (16 channels for Memory-to-memory DMA, 16 channels for Peripheral DMA)
Supports 14 8 key matrix
Configurable GPIOs
Real time clock, PLL, timer with PWM, and watch dog timer
Multi-core timer support for accurate tick time in power down mode (except sleep mode)
Memory Subsystem
Asynchronous SRAM/ ROM/ NOR interface with x8 or x16 data bus
NAND interface with x8 data bus
LPDDR2 interface (800 Mbps/pin DDR)
Embedded GPS/AGPS/GLONASS.
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