lowlevel_init 函数分析
2024-04-17 05:47:48
lowlevel_init函数主要用做底层的初始化，在start.S中确定启动介质后就要调用这个函数。uboo\board\samsung\x210/lowlevel_init.S
文章目录
- 压栈
- 检测复位状态
- IO状态恢复
- 关看门狗
- 供电锁存
- 初始化时钟
- 初始化DDR（动态内存）
- 初始化串口
- 初始化tzpc_init
- 打印K
- 出栈
- 整体
压栈
#include <config.h>
#include <version.h>#include <s5pc110.h>
#include "smdkc110_val.h"_TEXT_BASE:.word TEXT_BASE.globl lowlevel_init
lowlevel_init:push {lr} @@压栈，调用之前有设置栈，所以才能压栈
检测复位状态
/* check reset status */ @@检测复位状态;复位状态分为多种冷启动热启动休眠状态@@判断复位状态;不同的状态硬件的状态不一样比如冷启动DDR还没有初始化ldr r0, =(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET)ldr r1, [r0]cmp r1, #0x10000beq wakeup_reset_precmp r1, #0x80000beq wakeup_reset_from_didle
IO状态恢复
/* IO Retention release */ @@IO状态恢复ldr r0, =(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)ldr r1, [r0]ldr r2, =IO_RET_RELorr r1, r1, r2str r1, [r0]
关看门狗
/* Disable Watchdog */ @@关看门狗ldr r0, =ELFIN_WATCHDOG_BASE /* 0xE2700000 */mov r1, #0str r1, [r0]
供电锁存
/* PS_HOLD pin(GPH0_0) set to high */ @@供电锁存ldr r0, =(ELFIN_CLOCK_POWER_BASE + PS_HOLD_CONTROL_OFFSET)ldr r1, [r0]orr r1, r1, #0x300 @@两步，因为一步是非法立即数orr r1, r1, #0x1 @@str r1, [r0]
初始化时钟
/* when we already run in ram, we don't need to relocate U-Boot.* and actually, memory controller must be configured before U-Boot* is running in ram.*/ @@判断当前代码执行的地址;是通过代码运行的地址就能知道是否是冷启动，要不要 初始化DDRldr r0, =0xff000fffbic r1, pc, r0 /* r0 <- current base addr of code */ @@ r1 = pc & ~r0 ;运行地址ldr r2, _TEXT_BASE /* r1 <- original base addr in ram */ @@获取链接地址bic r2, r2, r0 /* r0 <- current base addr of code */cmp r1, r2 /* compare r0, r1 */beq 1f /* r0 == r1 then skip sdram init */ @@ 1 是标号 f 向下找@@通过上边的代码判断要不要执行下边这两个函数/* init system clock */ @@初始化时钟bl system_clock_init
初始化DDR（动态内存）
/* Memory initialize */ @@初始化DDR（初始化动态内存）bl mem_ctrl_asm_init
初始化串口
1:/* for UART */bl uart_asm_init @@初始化串口
初始化tzpc_init
bl tzpc_init
打印K
/* Print 'K' */ldr r0, =ELFIN_UART_CONSOLE_BASEldr r1, =0x4b4b4b4bstr r1, [r0, #UTXH_OFFSET]
出栈
pop {pc}整体
/** Memory Setup stuff - taken from blob memsetup.S** Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)** Modified for the Samsung SMDK2410 by* (C) Copyright 2002* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>** See file CREDITS for list of people who contributed to this* project.** This program is free software; you can redistribute it and/or* modify it under the terms of the GNU General Public License as* published by the Free Software Foundation; either version 2 of* the License, or (at your option) any later version.** This program is distributed in the hope that it will be useful,* but WITHOUT ANY WARRANTY; without even the implied warranty of* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the* GNU General Public License for more details.** You should have received a copy of the GNU General Public License* along with this program; if not, write to the Free Software* Foundation, Inc., 59 Temple Place, Suite 330, Boston,* MA 02111-1307 USA*/#include <config.h>
#include <version.h>#include <s5pc110.h>
#include "smdkc110_val.h"_TEXT_BASE:.word TEXT_BASE.globl lowlevel_init
lowlevel_init:push {lr} @@压栈，调用之前有设置栈，所以才能压栈/* check reset status */ @@检测复位状态;复位状态分为多种冷启动热启动休眠状态@@判断复位状态;不同的状态硬件的状态不一样比如冷启动DDR还没有初始化ldr r0, =(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET)ldr r1, [r0]cmp r1, #0x10000beq wakeup_reset_precmp r1, #0x80000beq wakeup_reset_from_didle/* IO Retention release */ @@IO状态恢复ldr r0, =(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)ldr r1, [r0]ldr r2, =IO_RET_RELorr r1, r1, r2str r1, [r0]/* Disable Watchdog */ @@关看门狗ldr r0, =ELFIN_WATCHDOG_BASE /* 0xE2700000 */mov r1, #0str r1, [r0]/* SRAM(2MB) init for SMDKC110 *//* GPJ1 SROM_ADDR_16to21 */ldr r0, =ELFIN_GPIO_BASEldr r1, [r0, #GPJ1CON_OFFSET]bic r1, r1, #0xFFFFFFldr r2, =0x444444orr r1, r1, r2str r1, [r0, #GPJ1CON_OFFSET]ldr r1, [r0, #GPJ1PUD_OFFSET]ldr r2, =0x3ffbic r1, r1, r2str r1, [r0, #GPJ1PUD_OFFSET]/* GPJ4 SROM_ADDR_16to21 */ldr r1, [r0, #GPJ4CON_OFFSET]bic r1, r1, #(0xf<<16)ldr r2, =(0x4<<16)orr r1, r1, r2str r1, [r0, #GPJ4CON_OFFSET]ldr r1, [r0, #GPJ4PUD_OFFSET]ldr r2, =(0x3<<8)bic r1, r1, r2str r1, [r0, #GPJ4PUD_OFFSET]/* CS0 - 16bit sram, enable nBE, Byte base address */ldr r0, =ELFIN_SROM_BASE /* 0xE8000000 */mov r1, #0x1str r1, [r0]/* PS_HOLD pin(GPH0_0) set to high */ @@供电锁存ldr r0, =(ELFIN_CLOCK_POWER_BASE + PS_HOLD_CONTROL_OFFSET)ldr r1, [r0]orr r1, r1, #0x300 @@两步，因为一步是非法立即数orr r1, r1, #0x1 @@str r1, [r0]/* when we already run in ram, we don't need to relocate U-Boot.* and actually, memory controller must be configured before U-Boot* is running in ram.*/ @@判断当前代码执行的地址;是通过代码运行的地址就能知道是否是冷启动，要不要 初始化DDRldr r0, =0xff000fffbic r1, pc, r0 /* r0 <- current base addr of code */ @@ r1 = pc & ~r0 ;运行地址ldr r2, _TEXT_BASE /* r1 <- original base addr in ram */ @@获取链接地址bic r2, r2, r0 /* r0 <- current base addr of code */cmp r1, r2 /* compare r0, r1 */beq 1f /* r0 == r1 then skip sdram init */ @@ 1 是标号 f 向下找@@通过上边的代码判断要不要执行下边这两个函数/* init system clock */ @@初始化时钟bl system_clock_init/* Memory initialize */ @@初始化DDR（初始化动态内存）bl mem_ctrl_asm_init1:/* for UART */bl uart_asm_init @@初始化串口bl tzpc_init #if defined(CONFIG_ONENAND)bl onenandcon_init
#endif#if defined(CONFIG_NAND)/* simple init for NAND */bl nand_asm_init
#endif/* check reset status */ldr r0, =(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET)ldr r1, [r0]bic r1, r1, #0xfffeffffcmp r1, #0x10000beq wakeup_reset_pre/* ABB disable */ldr r0, =0xE010C300orr r1, r1, #(0x1<<23)str r1, [r0]/* Print 'K' */ldr r0, =ELFIN_UART_CONSOLE_BASEldr r1, =0x4b4b4b4bstr r1, [r0, #UTXH_OFFSET]pop {pc}wakeup_reset_from_didle:/* Wait when APLL is locked */ldr r0, =ELFIN_CLOCK_POWER_BASE
lockloop:ldr r1, [r0, #APLL_CON0_OFFSET]and r1, r1, #(1<<29)cmp r1, #(1<<29)bne lockloopbeq exit_wakeupwakeup_reset_pre:mrc p15, 0, r1, c1, c0, 1 @Read CP15 Auxiliary control registerand r1, r1, #0x80000000 @Check L2RD is disable or notcmp r1, #0x80000000 bne wakeup_reset @if L2RD is not disable jump to wakeup_reset bl disable_l2cachebl v7_flush_dcache_all/* L2 cache enable at sleep.S of kernel* bl enable_l2cache */wakeup_reset:/* init system clock */bl system_clock_initbl mem_ctrl_asm_initbl tzpc_init
#if defined(CONFIG_ONENAND)bl onenandcon_init
#endif
#if defined(CONFIG_NAND)bl nand_asm_init
#endifexit_wakeup:/*Load return address and jump to kernel*/ldr r0, =(INF_REG_BASE+INF_REG0_OFFSET)ldr r1, [r0] /* r1 = physical address of s5pc110_cpu_resume function*/mov pc, r1 /*Jump to kernel */nopnop/** system_clock_init: Initialize core clock and bus clock.* void system_clock_init(void)*/
system_clock_init:ldr r0, =ELFIN_CLOCK_POWER_BASE @@0xe0100000;APLL_LOCK寄存器/* Set Mux to FIN */ldr r1, =0x0str r1, [r0, #CLK_SRC0_OFFSET] @@CLK_SRC0 寄存器赋值为零ldr r1, =APLL_LOCKTIME_VALstr r1, [r0, #APLL_LOCK_OFFSET] @@APLL_LOCK 寄存器 ,把他的分频系数设置为（E10）3600/********lxg added*********************/ldr r0, =ELFIN_CLOCK_POWER_BASE @@0xe010000;ldr r1, =MPLL_LOCKTIME_VAL @@0x04;str r1, [r0, #MPLL_LOCK_OFFSET] @@0xe010004;MPLL_LOCK 寄存器,把他的分频系数设置为（E10）3600/********end*********************//* Disable PLL */
#if defined(CONFIG_CHECK_MPLL_LOCK)
retryloop:
#endifldr r1, =0x0str r1, [r0, #APLL_CON0_OFFSET] @@APLL_CON0 寄存器 赋值为零， 禁止ldr r1, =0x0str r1, [r0, #MPLL_CON_OFFSET] @@MPLL_CON 寄存器 赋值为零，禁止ldr r1, =0x0str r1, [r0, #MPLL_CON_OFFSET] @@奇怪ldr r1, [r0, #CLK_DIV0_OFFSET] @@读取CLK_DIV0 寄存器的地址ldr r2, =CLK_DIV0_MASK @@r2 = 0x7fffffffbic r1, r1, r2 @@r1 = r1 & ~r2 清零ldr r2, =CLK_DIV0_VALorr r1, r1, r2str r1, [r0, #CLK_DIV0_OFFSET]ldr r1, =APLL_VALstr r1, [r0, #APLL_CON0_OFFSET]ldr r1, =MPLL_VALstr r1, [r0, #MPLL_CON_OFFSET]ldr r1, =VPLL_VALstr r1, [r0, #VPLL_CON_OFFSET]/*******lxg added***********************/ldr r1, =EPLL_VALstr r1, [r0, #EPLL_CON_OFFSET]/*******lxg added***********************/ldr r1, [r0, #CLK_DIV1_OFFSET]ldr r2, =CLK_DIV1_MASKbic r1, r1, r2ldr r2, =CLK_DIV1_VALorr r1, r1, r2str r1, [r0, #CLK_DIV1_OFFSET]ldr r1, [r0, #CLK_DIV2_OFFSET]ldr r2, =CLK_DIV2_MASKbic r1, r1, r2ldr r2, =CLK_DIV2_VALorr r1, r1, r2str r1, [r0, #CLK_DIV2_OFFSET]ldr r1, [r0, #CLK_DIV4_OFFSET]ldr r2, =CLK_DIV4_MASKbic r1, r1, r2ldr r2, =CLK_DIV4_VALorr r1, r1, r2str r1, [r0, #CLK_DIV4_OFFSET]ldr r1, [r0, #CLK_DIV6_OFFSET]ldr r2, =CLK_DIV6_MASKbic r1, r1, r2ldr r2, =CLK_DIV6_VALorr r1, r1, r2str r1, [r0, #CLK_DIV6_OFFSET]/*******end*****************//*******end*****************/
#if defined(CONFIG_EVT1)ldr r1, =AFC_ONstr r1, [r0, #APLL_CON1_OFFSET]
#endifmov r1, #0x10000
1: subs r1, r1, #1bne 1b#if defined(CONFIG_CHECK_MPLL_LOCK)/* MPLL software workaround */ldr r1, [r0, #MPLL_CON_OFFSET]orr r1, r1, #(1<<28)str r1, [r0, #MPLL_CON_OFFSET]mov r1, #0x100
1: subs r1, r1, #1bne 1bldr r1, [r0, #MPLL_CON_OFFSET]and r1, r1, #(1<<29)cmp r1, #(1<<29)bne retryloop/* H/W lock detect disable */ldr r1, [r0, #MPLL_CON_OFFSET]bic r1, r1, #(1<<28)str r1, [r0, #MPLL_CON_OFFSET]
#endifldr r1, [r0, #CLK_SRC0_OFFSET]//ldr r2, =0x10001111 //lxg changed.ldr r2, =0x00000111orr r1, r1, r2str r1, [r0, #CLK_SRC0_OFFSET]// added by terry 2012.12.4 for camera ldr r1, [r0, #CLK_SRC1_OFFSET]bic r1, r1, #(0xf<<12)orr r1, r1, #(0x1<<12) //0001 XusbXTIstr r1, [r0, #CLK_SRC1_OFFSET]#if defined(CONFIG_MCP_AC)/* CLK_SRC6[25:24] -> OneDRAM clock sel = MPLL */ldr r1, [r0, #CLK_SRC6_OFFSET]bic r1, r1, #(0x3<<24)orr r1, r1, #0x01000000str r1, [r0, #CLK_SRC6_OFFSET]/* CLK_DIV6[31:28] -> 4=1/5, 3=1/4(166MHZ@667MHz), 2=1/3 */ldr r1, [r0, #CLK_DIV6_OFFSET]bic r1, r1, #(0xF<<28)bic r1, r1, #(0x7<<12) @; ONENAND_RATIO: 0orr r1, r1, #0x30000000str r1, [r0, #CLK_DIV6_OFFSET]#elif defined (CONFIG_MCP_H)/* CLK_SRC6[25:24] -> OneDRAM clock sel = 00:SCLKA2M, 01:SCLKMPLL */ldr r1, [r0, #CLK_SRC6_OFFSET]bic r1, r1, #(0x3<<24)orr r1, r1, #0x00000000str r1, [r0, #CLK_SRC6_OFFSET]/* CLK_DIV6[31:28] -> 4=1/5, 3=1/4(166MHZ@667MHz), 2=1/3 */ldr r1, [r0, #CLK_DIV6_OFFSET]bic r1, r1, #(0xF<<28)bic r1, r1, #(0x7<<12) @; ONENAND_RATIO: 0orr r1, r1, #0x00000000str r1, [r0, #CLK_DIV6_OFFSET] #elif defined (CONFIG_MCP_B) || defined (CONFIG_MCP_D)/* CLK_SRC6[25:24] -> OneDRAM clock sel = 00:SCLKA2M, 01:SCLKMPLL */ldr r1, [r0, #CLK_SRC6_OFFSET]bic r1, r1, #(0x3<<24)orr r1, r1, #0x01000000str r1, [r0, #CLK_SRC6_OFFSET]/* CLK_DIV6[31:28] -> 4=1/5, 3=1/4(166MHZ@667MHz), 2=1/3 */ldr r1, [r0, #CLK_DIV6_OFFSET]bic r1, r1, #(0xF<<28)bic r1, r1, #(0x7<<12) @; ONENAND_RATIO: 0orr r1, r1, #0x30000000str r1, [r0, #CLK_DIV6_OFFSET]#elif defined (CONFIG_MCP_SINGLE)/* CLK_DIV6 *//*ldr r1, [r0, #CLK_DIV6_OFFSET]bic r1, r1, #(0x7<<12) @; ONENAND_RATIO: 0str r1, [r0, #CLK_DIV6_OFFSET]*/ //lxg mask#endif mov pc, lr/** uart_asm_init: Initialize UART in asm mode, 115200bps fixed.* void uart_asm_init(void)*/
uart_asm_init:/* set GPIO(GPA) to enable UART */@ GPIO setting for UARTldr r0, =ELFIN_GPIO_BASEldr r1, =0x22222222str r1, [r0, #GPA0CON_OFFSET]ldr r1, =0x2222str r1, [r0, #GPA1CON_OFFSET]// HP V210 use. SMDK not use.
#if defined(CONFIG_VOGUES)ldr r1, =0x100str r1, [r0, #GPC0CON_OFFSET]ldr r1, =0x4str r1, [r0, #GPC0DAT_OFFSET]
#endifldr r0, =ELFIN_UART_CONSOLE_BASE @0xEC000000mov r1, #0x0str r1, [r0, #UFCON_OFFSET]str r1, [r0, #UMCON_OFFSET]mov r1, #0x3str r1, [r0, #ULCON_OFFSET]ldr r1, =0x3c5str r1, [r0, #UCON_OFFSET]ldr r1, =UART_UBRDIV_VALstr r1, [r0, #UBRDIV_OFFSET]ldr r1, =UART_UDIVSLOT_VALstr r1, [r0, #UDIVSLOT_OFFSET]ldr r1, =0x4f4f4f4fstr r1, [r0, #UTXH_OFFSET] @'O'mov pc, lr/** Nand Interface Init for SMDKC110*/
nand_asm_init:/* Setting GPIO for NAND *//* This setting is NAND initialze code at booting time in iROM. */ldr r0, =ELFIN_GPIO_BASEldr r1, [r0, #MP01CON_OFFSET]bic r1, r1, #(0xf<<8)orr r1, r1, #(0x3<<8)str r1, [r0, #MP01CON_OFFSET]ldr r1, [r0, #MP01PUD_OFFSET]bic r1, r1, #(0x3<<4)str r1, [r0, #MP01PUD_OFFSET]ldr r1, [r0, #MP03CON_OFFSET]bic r1, r1, #0xFFFFFFldr r2, =0x22222222orr r1, r1, r2str r1, [r0, #MP03CON_OFFSET]ldr r1, [r0, #MP03PUD_OFFSET]ldr r2, =0x3fffbic r1, r1, r2str r1, [r0, #MP03PUD_OFFSET]ldr r0, =ELFIN_NAND_BASEldr r1, [r0, #NFCONF_OFFSET]ldr r2, =0x777Fbic r1, r1, r2ldr r2, =NFCONF_VALorr r1, r1, r2str r1, [r0, #NFCONF_OFFSET]ldr r1, [r0, #NFCONT_OFFSET]ldr r2, =0x707C7bic r1, r1, r2ldr r2, =NFCONT_VALorr r1, r1, r2str r1, [r0, #NFCONT_OFFSET]ldr r1, [r0, #NFCONF_OFFSET]orr r1, r1, #0x70orr r1, r1, #0x7700str r1, [r0, #NFCONF_OFFSET]ldr r1, [r0, #NFCONT_OFFSET]orr r1, r1, #0x03str r1, [r0, #NFCONT_OFFSET]mov pc, lr/** Setting TZPC[TrustZone Protection Controller]*/
tzpc_init:ldr r0, =ELFIN_TZPC0_BASEmov r1, #0x0str r1, [r0]mov r1, #0xffstr r1, [r0, #TZPC_DECPROT0SET_OFFSET]str r1, [r0, #TZPC_DECPROT1SET_OFFSET]str r1, [r0, #TZPC_DECPROT2SET_OFFSET] ldr r0, =ELFIN_TZPC1_BASEstr r1, [r0, #TZPC_DECPROT0SET_OFFSET]str r1, [r0, #TZPC_DECPROT1SET_OFFSET]str r1, [r0, #TZPC_DECPROT2SET_OFFSET] ldr r0, =ELFIN_TZPC2_BASEstr r1, [r0, #TZPC_DECPROT0SET_OFFSET]str r1, [r0, #TZPC_DECPROT1SET_OFFSET]str r1, [r0, #TZPC_DECPROT2SET_OFFSET]str r1, [r0, #TZPC_DECPROT3SET_OFFSET] ldr r0, =ELFIN_TZPC3_BASEstr r1, [r0, #TZPC_DECPROT0SET_OFFSET]str r1, [r0, #TZPC_DECPROT1SET_OFFSET]str r1, [r0, #TZPC_DECPROT2SET_OFFSET] mov pc, lr/** OneNAND Interface Init*/
onenandcon_init:@; GPIO setting for OneNANDldr r0, =ELFIN_GPIO_BASE @0xE0200000ldr r1, [r0, #MP01CON_OFFSET]orr r1, r1, #0x00550000str r1, [r0, #MP01CON_OFFSET]ldr r1, [r0, #MP03CON_OFFSET]orr r1, r1, #0x0550orr r1, r1, #0x00550000str r1, [r0, #MP03CON_OFFSET]ldr r1, =0xFFFFstr r1, [r0, #MP01DRV_SR_OFFSET]str r1, [r0, #MP03DRV_SR_OFFSET]str r1, [r0, #MP06DRV_SR_OFFSET]str r1, [r0, #MP07DRV_SR_OFFSET]wait_orwb:@; Read ONENAND_IF_STATUSldr r0, =ELFIN_ONENANDCON_BASE @; 0xB0600000ldr r1, [r0, #ONENAND_IF_STATUS_OFFSET]bic r1, r1, #0xFFFFFFFEcmp r1, #0x0@; ORWB != 0x0bne wait_orwb@; write new configuration to onenand system configuration1 registerldr r1, =0xF006 @; Sync.ldr r2, =(ELFIN_ONENAND_BASE+0x1E442) @; 0x1E442(REG_SYS_CONF1)strh r1, [r2]@; read one dummy halfwordldrh r1, [r2]ldrh r1, [r2]@; write new configuration to ONENAND_IF_CTRLldr r0, =ELFIN_ONENANDCON_BASE @; 0xB0600000@;ldr r1, =0x2F006 @; ONENAND_IF_CTRL_REG_VAL (GCE off)ldr r1, =0x402F006 @; ONENAND_IF_CTRL_REG_VAL (GCE on)str r1, [r0, #ONENAND_IF_CTRL_OFFSET]mov pc, lr#ifdef CONFIG_ENABLE_MMU#ifdef CONFIG_MCP_SINGLE
/** MMU Table for SMDKC110* 0x0000_0000 -- 0xBFFF_FFFF => Not Allowed* 0xB000_0000 -- 0xB7FF_FFFF => A:0xB000_0000 -- 0xB7FF_FFFF* 0xC000_0000 -- 0xC7FF_FFFF => A:0x3000_0000 -- 0x37FF_FFFF* 0xC800_0000 -- 0xDFFF_FFFF => Not Allowed* 0xE000_0000 -- 0xFFFF_FFFF => A:0xE000_0000 -- 0XFFFF_FFFF*//* form a first-level section entry */
.macro FL_SECTION_ENTRY base,ap,d,c,b.word (\base << 20) | (\ap << 10) | \(\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1)
.endm
.section .mmudata, "a".align 14// the following alignment creates the mmu table at address 0x4000..globl mmu_table
mmu_table:.set __base,0// Access for iRAM.rept 0x100FL_SECTION_ENTRY __base,3,0,0,0.set __base,__base+1.endr// Not Allowed.rept 0x200 - 0x100.word 0x00000000.endr.set __base,0x200// should be accessed.rept 0x600 - 0x200FL_SECTION_ENTRY __base,3,0,1,1.set __base,__base+1.endr.rept 0x800 - 0x600.word 0x00000000.endr.set __base,0x800// should be accessed.rept 0xb00 - 0x800FL_SECTION_ENTRY __base,3,0,0,0.set __base,__base+1.endr/* .rept 0xc00 - 0xb00.word 0x00000000.endr */.set __base,0xB00.rept 0xc00 - 0xb00FL_SECTION_ENTRY __base,3,0,0,0.set __base,__base+1.endr// 0xC000_0000映射到0x2000_0000.set __base,0x300//.set __base,0x200// 256MB for SDRAM with cacheable.rept 0xD00 - 0xC00FL_SECTION_ENTRY __base,3,0,1,1.set __base,__base+1.endr// access is not allowed.@.rept 0xD00 - 0xC80@.word 0x00000000@.endr.set __base,0xD00// 1:1 mapping for debugging with non-cacheable.rept 0x1000 - 0xD00FL_SECTION_ENTRY __base,3,0,0,0.set __base,__base+1.endr #else // CONFIG_MCP_AC, CONFIG_MCP_H, CONFIG_MCP_B/** MMU Table for SMDKC110* 0x0000_0000 -- 0xBFFF_FFFF => Not Allowed* 0xB000_0000 -- 0xB7FF_FFFF => A:0xB000_0000 -- 0xB7FF_FFFF* 0xC000_0000 -- 0xC7FF_FFFF => A:0x3000_0000 -- 0x37FF_FFFF* 0xC800_0000 -- 0xDFFF_FFFF => Not Allowed* 0xE000_0000 -- 0xFFFF_FFFF => A:0xE000_0000 -- 0XFFFF_FFFF*//* form a first-level section entry */
.macro FL_SECTION_ENTRY base,ap,d,c,b.word (\base << 20) | (\ap << 10) | \(\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1)
.endm
.section .mmudata, "a".align 14// the following alignment creates the mmu table at address 0x4000..globl mmu_table
mmu_table:.set __base,0// Access for iRAM.rept 0x100FL_SECTION_ENTRY __base,3,0,0,0.set __base,__base+1.endr// Not Allowed.rept 0x300 - 0x100.word 0x00000000.endr.set __base,0x300// should be accessed.rept 0x400 - 0x300//.rept 0x350 - 0x300FL_SECTION_ENTRY __base,3,0,1,1.set __base,__base+1.endr// Not Allowed//.rept 0x400 - 0x350//.word 0x00000000//.endr// DRAM - DMC1 area - used for STL_write : djpark (20090729).set __base,0x400// should be accessed.rept 0x500 - 0x400FL_SECTION_ENTRY __base,3,0,1,1.set __base,__base+1.endr.rept 0x800 - 0x500.word 0x00000000.endr.set __base,0x800// should be accessed.rept 0xb00 - 0x800FL_SECTION_ENTRY __base,3,0,0,0.set __base,__base+1.endr.set __base,0xB00.rept 0xc00 - 0xb00FL_SECTION_ENTRY __base,3,0,0,0.set __base,__base+1.endr.set __base,0x300// 80MB for SDRAM with cacheable.rept 0xd00 - 0xC00//.rept 0xC50 - 0xC00FL_SECTION_ENTRY __base,3,0,1,1.set __base,__base+1.endr// Not Allowed@.rept 0xD00 - 0xC80@.word 0x00000000@.endr// Not Allowed//.rept 0xD00 - 0xC50//.word 0x00000000//.endr.set __base,0xD00// 1:1 mapping for debugging with non-cacheable.rept 0x1000 - 0xD00FL_SECTION_ENTRY __base,3,0,0,0.set __base,__base+1.endr#endif
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