CE162 Lec06

Multiplexer / Data selector
- 4选1数据选择器 / Four input Multiplexer
- Other applications of Multiplexers
Decoder
- 3线-8线译码器
- 2线-4线译码器
- Application
Digital signals
- Digital Representation of Signals
- Bandwidth and Sampling Rate
- Aliasing（混叠）
- Electronic Sampling: A basic Sample and Hold circuit
- Practical Sample and Hold Circuit
- Performance
- Quantization

Multiplexer / Data selector

是一种数据开关，用于从多个数据源中选择其中一路传送到公共的数据线上，能够实现这种功能的逻辑电路称为数据选择器或多路开关（Multiplexer ）
Its original application as a way of transmitting digital data from a number of sources down a single channel, by enabling each source in turn onto the channel
完成从一组输入数据中选出某一个的功能
即在通道选择信号的控制下，将多个通道的数据分时传送到公共的数据通道上

4选1数据选择器 / Four input Multiplexer

One of inputs I0 – I3 is routed to (被路由到) output, Y, depending on inputs A and B
AB确定时，相当于输入I的某一路确定
Input G enables or disables the whole device; can be used when multiplexers are cascaded (级联) to handle more inputs
Truth Table of four input multiplexer
表达式
- Y = I₀ A‾\overline{A}A B‾\overline{B}B G‾\overline{G}G + I₁A‾\overline{A}A B G‾\overline{G}G+ I₂ A B‾\overline{B}B G‾\overline{G}G+ I₃ A B G‾\overline{G}G
- Y = I₀m₀ + I₁m₁ + I₂m₂ + I₃m₃ （m_i为AB构成的最小项）
Logic diagram for a four input multiplexer
Actual circuits may have two or more
strobe/enable inputs, to facilitate cascading devices and separate the strobe and enable functions
The output may also be available in true and complement forms

Other applications of Multiplexers

Multiplexers can implement combinational logic directly from Truth Table to avoid wiring individual gates, - known as a ‘random logic’ implementation.

The same basic circuit element (the multiplexer) can be ‘programmed’ to realize any required function of a certain number of inputs.

example
- Suppose we have an 8 to 1 multiplexer and want to generate an ‘odd’ parity bit from three inputs ABC
- connect a signal to each data input
Variable Entered K-Map technique
（并不知道以上这一部分在说什么）

Decoder

A device to detect a specific bit combination (a code).
In general: n input lines, 2ⁿ output lines to indicate presence of one or more n-bit codes.
A simple decoder can be achieved with a combination of NOT gates and a multi-input AND gate.
More generally, combinations of multiplxers and demultiplexers may be used as decoders.
‘decoder’ = ‘demultiplexer’

3线-8线译码器

逻辑符号
真值表
To activate the outputs, G1 must be HIGH and BOTH G2A and G2B must be LOW

2线-4线译码器

逻辑图

Can be implemented with multiple AND gates and NOT gates

Application

part of RS232 receiver
logic function generator
Interpret an instruction register
memory matrix

Digital signals

Digital Representation of Signals

All digital systems process data in discrete chunks
Advantages
- Error-free transmission （无误传输）
- Processing, transmission and storage. Many signal processing operations can only be done on digitised signals. Digital signals can usually be ‘compressed’, meaning the amount of data actually required is much less than the raw sampling process generates （省）

Bandwidth and Sampling Rate

It is the range of frequencies present in the raw analogue signal that determines the minimum required sampling rate
Nyquist’s Theorem: A signal can be reproduced exactly from samples taken at a rate that is at least twice the highest frequency found in the signal
Ideal: the highest frequency corresponds to the signal bandwidth
In practice, for theoretical reasons it is not possible to define exactly what is a signal’s bandwidth, so an approximation is used instead. Any components above the nominal bandwidth (标称带宽) are regarded as ‘insignificant’
This is reflected in practice by choosing sample rates slightly higher than the Nyquist figure

Aliasing（混叠）

This phenomenon of one signal ‘pretending’ to be another is called aliasing, and is a fundamental property (and problem!) in all sampled data systems that needs to be taken into account at an early stage in a system design
Sampling a signal at less than the Nyquist rate f_s < 2f_c. Aliasing occurs
Sampling the rate at more that the Nyquist rate f_s > 2f_c. No aliasing

Electronic Sampling: A basic Sample and Hold circuit

Conversion from analogue to digital form needs away of temporarily storing the input so conversion can be carried out（从模拟到数字的转换需要暂时储存输入才可以进行）

The circuit does this by briefly closing an electronic switch that connects input signal to a capacitor（该电路通过短暂闭合一个电子开关来实现这一点，该电子开关将输入信号连接到电容上）

While switch is closed (a short circuit), the capacitor voltage tracks the input（跟踪输入）, then freezes it when the switch opens

For this circuit to work:

The internal resistance（内阻）of the signal source needs to be as low as possible (ideally zero)

The ‘ON’ resistance of the switch needs to be as low as possible, and its ‘OFF’ resistance infinite

The input resistance of the amplifier needs to as high as possible (ideally infinite)

In practice, these requirements can only be met approximately

Practical Sample and Hold Circuit

开关：an n-channel Junction Field-Effect Transistor

电路适用：audio frequencies

Sample pulse的极值 = power supply rail voltages (say ±12 V)

Ground = 0 V

负：diode conducts（二极管导通）, FET gate 最大负电位，source-drain connection打开，当模拟输入信号的平均电平在0v左右时，电路工作得最好。

正：diode is cut off, the resistor R (≈ 22 k) 确保gate和analogue input电位相等（即跟踪输入电压）（跟踪：两路关联）FET acts as a moderately low resistance（中低等电阻），电容器将充电/放电直到与输入电压相同（理想情况下，当FET导电时，电容上的电压实际上会跟踪输入电压）。在采样脉冲的下降沿，FET is again cut off，输入电压的值at that instant will be retained across the capacitor.

Performance

Raw samples（原始样本）: This is achieved by replacing the hold capacitor with a resistor, and demonstrates that sampling is a kind of modulation, where the sample pulse train is multiplied by the input signal.（这是通过用电阻代替保持电容来实现的，并证明了采样是一种调制，采样脉冲序列乘以输入信号。）
Sample-and-hold. Here the ‘hold’ capacitor is in place; otherwise conditions are the same
In both pictures, the ‘voltage tracking’ behavior during the sample pulse can just be seen.

Filter output is inverted and delayed with respect to the unsampledoriginal（滤波器输出相对于未采样的原始值是反向的和延迟的）

Quantization

Quantization= procedure of converting a discrete-time continuous-amplitude signal (after sampling) into discrete-time discrete-amplitude signal (Divide the amplitude range into equal intervals)（将离散时间连续幅值信号(采样后)转换为离散时间离散幅值信号的过程）

If we want to represent a signal in a computer, it has to be as a binary number of some fixed number of bits, n, leading to an amplitude resolution of N = 2ⁿ levels.（E.g. for n = 8 bits, N = 256）

Quality (reducing distortion) improves with the number of bits, but cost and complexity also increase, so the minimum number that gives acceptable quality is used.（质量(减少失真)随着比特数的增加而提高，但成本和复杂性也在增加，因此使用了能提供可接受质量的最小数量。）
电话语音八位采样

Signal to Noise ration (SNR) （信噪比）：信号功率与噪声功率的比值
（这里的噪声产生原因是量子化的引入）

Quantization levels: The value of each sample is represented by a value selected from a finite set of possible values
Quantization width = (Vmax-Vmin)/(no. of levels –1)
Quantization error: 量化过程中由于舍入到最接近的水平而产生的误差

Coding
In the coding process, each discrete value（离散值）is represented by a certain number of bits
Relationship between bits and levels: 2^{number-of-bits} >= no. of levels

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