library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity cnt10 is

port(clk:in std_logic;

clr:in std_logic;

cs :in std_logic;

qq :buffer std_logic_vector(3 downto 0);

co :out std_logic);

end cnt10;

architecture one of cnt10 is

begin

process(clk,clr,cs)

begin

if (clr='1') then

qq<="0000";

elsif (clk'event and clk='1') then

if (cs='1') then

if (qq=9) then

qq<="0000";

else

qq<=qq+1;

end if;

end if;

end if;

end process;

process(qq)

begin

if (qq=9) then

co<= '0';

else

co<='1';

end if;

end process;

end;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY LATCH4 IS

PORT(le: IN STD_LOGIC;

dd: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

qq: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END LATCH4;

ARCHITECTURE one OF LATCH4 IS

BEGIN

PROCESS(le,dd)

BEGIN

IF (le='1') THEN

qq<=dd;

END IF;

END PROCESS;

END one;

library ieee;

use ieee.std_logic_1164.all;

entity decoder is

port(din：in std_logic_vector(3 downto 0);

led7s：out std_logic_vector(6 downto 0)

);

End;

architecture one of decoder is

begin

process(din)

begin

case din is

when "0000"=>led7s<="1000000";

when "0001"=>led7s<="1111001";

when "0010"=>led7s<="0100100";

when"0011"=>led7s<="0110000";

when"0100"=>led7s<="0011001";

when"0101"=>led7s<="0010010";

when"0110"=>led7s<="0000010";

when"0111"=>led7s<="1111000";

when"1000"=>led7s<="0000000";

when"1001"=>led7s<="0010000";

when"1010"=>led7s<="0001000";

when"1011"=>led7s<="0000011";

when"1100"=>led7s<="1000110";

when"1101"=>led7s<="0100001";

when"1110"=>led7s<="0000110";

when"1111"=>led7s<="0001110";

when others=>led7s<=null;

end case;

end process;

end;

library ieee;

use ieee.std_logic_1164.all;

entity control is

port(clk: in std_logic;

cs,clr,le: out std_logic);

end control;

architecture behav of control is

signal current_state,next_state:std_logic_vector(3 downto 0);

constant st0:std_logic_vector :="0011" ;

constant st1:std_logic_vector :="0010";

constant st2:std_logic_vector :="0110";

constant st3:std_logic_vector :="0111";

constant st4:std_logic_vector :="0101";

constant st5:std_logic_vector :="0100";

constant st6:std_logic_vector :="1100";

constant st7:std_logic_vector :="1101";

constant st8:std_logic_vector :="1111";

constant st9:std_logic_vector :="1110";

begin

com1:process(current_state)

begin

case current_state is

when st0=>next_state<=st1; clr<='1'; cs<='0'; le<='0';

when st1=>next_state<=st2; clr<='0'; cs<='1'; le<='0';

when st2=>next_state<=st3; clr<='0'; cs<='1'; le<='0';

when st3=>next_state<=st4; clr<='0'; cs<='1'; le<='0';

when st4=>next_state<=st5; clr<='0'; cs<='1'; le<='0';

when st5=>next_state<=st6; clr<='0'; cs<='1'; le<='0';

when st6=>next_state<=st7; clr<='0' ; cs<='1'; le<='0';

when st7=>next_state<=st8; clr<='0'; cs<='1'; le<='0';

when st8=>next_state<=st9; clr<='0'; cs<='1'; le<='0';

when st9=>next_state<=st0; clr<='0'; cs<='0'; le<='1';

when others=>next_state<=st0; clr<='0'; cs<='0'; le<='0';

end case;

end process com1;

reg: process(clk)

begin

if (clk'event and clk='1') then

current_state<=next_state;

end if;

end process reg;

end behav;