SPARTAN 6(XC6SLX9-TQG144) PCB Design

Power Distribution System

PCB Decoupling Capacitors

The impedance of the alternate network must be less
than or equal to that of the recommended network across frequencies from 100 KHz to
500 MHz.
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0805 Ceramic Capacitor

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0402 Ceramic Capacitor

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Basic PDS Principles

Peak-to-Peak VRIPPLE < Vcc * 10%.

Capacitor Parasitic Inductance

Requirements for choosing decoupling capacitors:

• For a specific capacitance value, choose the smallest package available.

• For a specific package size (essentially a fixed inductance value), choose the highest
capacitance value available in that package.

Surface-mount chip capacitors are the smallest capacitors available and are a good choice
for discrete decoupling capacitors:

• For values from 100 µF to very small values such as 0.01 µF, X7R or X5R type
capacitors are usually used. These capacitors have a low parasitic inductance and a
low ESR, with an acceptable temperature characteristic.

• For larger values, such as 100 µF to 1000 µF, tantalum capacitors are used. These
capacitors have a low parasitic inductance and a medium ESR, giving them a low Q
factor and consequently a very wide range of effective frequencies.

PCB Current Path Inductance

PCB layout engineers often try to squeeze more parts into a small area by sharing vias
among multiple capacitors. This technique should not be used under any circumstances. PDS
improvement is very small when a second capacitor is connected to an existing capacitor’s
vias. For a larger improvement, reduce the total number of capacitors and maintain a oneto-one ratio of lands to vias.

Plane Inductance

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FPGA Mounting Inductance

The via field under an FPGA has many VCC and GND vias, and the total inductance is a
function of the proximity of one via to another:

• For core VCC supplies (VCCINT and VCCAUX), opposing current is between the VCC
and GND pins.

• For I/O VCC supplies (VCCO), opposing current is between any I/O and its return
current path, whether carried by a VCCO or GND pin.

To reduce parasitic inductance:

• VCCINT and GND are placed in a checkerboard arrangement in the center area of the
BGA packages.

• VCCO and GND pins are distributed among the I/O pins.

Capacitor Effective Frequency

ESL: parasitic inductance(ESL).

ESR: parasitic resistance(ESR).

To determine the capacitor’s total parasitic inductance in the system, LIS, the capacitor’s
parasitic inductance, LSELF, is added to the mounting’s parasitic inductance, LMOUNT:

LIS = LSELF + LMOUNT

For example, using X7R Ceramic Chip capacitor in 0402 body size:

C = 0.01 μF (selected by user)

LSELF = 0.9 nH (capacitor data sheet parameter)

FRSELF = 53 MHz (capacitor data sheet parameter)

LMOUNT = 0.8 nH (based on PCB mounting geometry)

To determine the effective in-system parasitic inductance (LIS), add the via parasitics:

LIS = LSELF + LMOUNT = 0.9 nH + 0.8 nH

LIS = 1.7 nH

The values from the example are used to determine the mounted capacitor resonant
frequency (FRIS). Using Equation 2-1:

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FRSELF is 53 MHz, but FRIS is lower at 38 MHz. The addition of mounting inductances
shifts the effective-frequency band down.

Capacitor Placement Background

Another delay of the same duration occurs when the compensation current from the
capacitor flows to the FPGA. For any transient current demand in the FPGA, a round-trip
delay occurs before any relief is seen at the FPGA.

• Negligible energy is transferred to the FPGA with placement distances greater than
one quarter of a demand frequency’s wavelength.

• Energy transferred to the FPGA increases from 0% at one-quarter of a wavelength to
100% at zero distance.

• Energy is transferred efficiently from the capacitor to the FPGA when capacitor
placement is at a fraction of a quarter wavelength of the FPGA power pins. This
fraction should be small because the capacitor is also effective at some frequencies
(shorter wavelengths) above its resonant frequency

One-tenth of a quarter wavelength is a good target for most practical applications and
leads to placing a capacitor within one-fortieth of a wavelength of the power pins it is
decoupling. The wavelength corresponds to the capacitor’s mounted resonant frequency,
FRIS.

Unconnected VCCO Pins

ESD: Electro Spark Detector

Leaving the VCCO pins of unused I/O banks floating reduces the level of ESD protection
on these pins and the I/O pins in the bank. ESD events at the unconnected solder balls in
the inner rows of a BGA pinout array are unlikely and not considered a high risk.
However, ESD events at exposed pins on the perimeter of a QFP-type package are likely.
In these packages, the VCCO pins of unused I/O banks should be connected to the VCCO of
a neighboring I/O bank.

SelectIO Signaling

SDR versus DDR Interfaces

The difference between Single Data Rate (SDR) and Double Data Rate (DDR) interfaces has
to do with the relationship of the data signals of a bus to the clock signal of that bus. In SDR
systems, data is only registered at the input flip-flops of a receiving device on either the
rising or the falling edge of the clock. One full clock period is equivalent to one bit time. In
DDR systems, data is registered at the input flip-flops of a receiving device on both the
rising and falling edges of the clock. One full clock period is equivalent to two bit times.
The distinction of SDR and DDR has nothing to do with whether the I/O standard carrying
the signals is single-ended or differential. A single-ended interface can be SDR or DDR,
and a differential interface can also be SDR or DDR.

PCB Materials and Traces

How Fast is Fast?

Signal edges contain frequency components called harmonics. Each harmonic is a multiple
of the signal frequency and has significant amplitude up to a frequency determined by
Equation 4-1:

f ≈ 0.35 / T Equation 4-1

Where:

f = Frequency in GHz

T = The smaller of signal rise (Tr) or fall (Tf) time in ns

Because dielectric losses in a PCB are frequency dependent, a bandwidth of concern must
be determined to find the total loss of the PCB. Frequencies must start at the operation
frequency and extend to the frequency in Equation 4-1. For example, a 10 Gb/s signal with
a 10 ps rise time has a bandwidth from 10 GHz to 35 GHz.

Trace Routing

The two traces of a differential pair must be length-matched to eliminate skew. Skew
creates mismatches in the common mode and reduces the differential voltage swing as a
result.

STRIPLINE
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MICROSTRIP
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Design of Transitions for High-Speed Signals

Time Domain Reflectometry

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Refer To Spartan-6 FPGA PCB Design and Pin Planning Guide