USB SS-PHY Tuning

1 USB 3.0 PIPE PHY
1.1 SS PHY电流源
CML电流源串联在NMOS管的Source中，电流是16 mA，所以差分电压摆幅是16 mA x (50 // 50) x 2 = 800 mV。

1.2 PIPE PHY数据线宽度
DWC_usb3_databook_2.50a.pdf
USB 3.0 PIPE PHY（SerDes = PCIe Gen2）的数据线宽度是可以设置的，最大宽度分别是Tx 32bit、Rx 32bit，需要根据PIPE PHY的接口频率来设置数据线宽度。如果PIPE PHY运行在128MHz，那么Tx和Rx的数据线宽度都是32bit；如果PIPE PHY运行在256MHz，那么Tx和Rx的数据线宽度都是16bit。

USB 3.0 Gen1的速度5Gbps，是指Tx和Rx的速率都是5Gbps（128MHz x 4bytes或者256MHz x 2bytes）。
USB 3.0 Gen1的速度5Gbps（625MB/s），协议开销（overhead）占用了20%带宽，所以实际有效速度是500MB/s。
USB 3.0 Tx或者Rx的传输速率虽然是5Gbps，但实际上数字信号的方波频率是2.5GHz（传输2个bit对应一个方波）。

Intel APL (Gen9, A39X0) 8-port MPH xHCI的物理层名字是ModPHY（High Speed I/O Modular Physical Layer for Intel USB 3.0）。

TI AM65x has 2 DWC3 controller instances. USB1 SerDes needs external 100MHz clock oscillator for SERDES0_REFCLKP and SERDES0_REFCLKN.

1.3 Lane polarity reversal
USB SS SerDes支持差分信号极性反转。

You can swap the SSTX and SSRX pairs but not the USB2 (D+/D-) pair. This is because, during SuperSpeed enumeration, certain training sequences (called TSEQs) are sent and the D10.2 symbol in this is used to detect if lane polarity inversion is done (refer to section 6.4.2 of the USB 3.0 spec). However, such lane inversion detection is not done in USB 2.0 enumeration.

1.4 Rx.Detect
Link层LTSSM会周期性驱动PHY的PIN TxDetectRx到高，让PHY做Receiver Detection。Receiver的SSRX+/-上各有一个等效的50欧姆下拉电阻，并联形成25欧姆电阻。
设备连接前的充放电时间常数T = R_Detect * C_Parasitic
设备连接后的充放电时间常数T = (R_Detect + R_Term) * (C_AC + C_Parasitic)
Probe SSTX+, you can see the 500mV Rx.Detect pulse without connecting device, its period is 13.75ms (72Hz), pulse width is less than 40us.

1.5 Redriver Rx.Detect
If Redriver detects receiver on its transmitter, then it assumes there is a valid termination. In this case, Redriver turns on its own Rx 50-ohm termination, this signals the xHCI to start Rx.Detect. Redriver does not include LTSSM, but Retimer includes LTSSM.

1.6 Electrical Idle
Electrical Idle means the differential voltage applied to the link is 0mV (no signaling). If there is 0mV differential, then the Rx cannot recover a clock and bit/symbol lock is lost.
In Logical Idle the Rx maintains bit/symbol lock because the Tx will send IDLE symbols. The IDLE symbols do not contain data and are thrown away by the Rx.

2 Link Layer
2.1 LTSSM
LTSSM has three main states, they are Detect, Polling and U (DPU). Refer to Figure 7-14 in page 190 of USB 3.0 spec.

SS.Disabled - 产生中断
SS.Inactive - 产生中断
Compliance Mode - 不产生中断
khubd：基于外部USB HUB设计
LFPS: OOB (Out-of-band) signal is used while the Gigabit transceivers are turned off (electrical idle)

Selected low-level topics regarding USB 3.x (SuperSpeed / SuperSpeedPlus)
http://xillybus.com/tutorials/usb-ltssm-lfps-power-management

2.2 Tx - Compliance mode
CP0 is sent by DUT Tx+/- firstly, when trigger device sends Ping.LFPS to DUT Rx+, then DUT will toggle CP1/CP7/CP8 to oscilloscope via Tx+/-.
CP1: SSC，调制三角波（30～33kHz）

Enter compliance mode :
1)  Plug in USB host cable w/o fixture connected
2)  Disable any power management features:
a.  echo on > /sys/bus/usb/usb1/power/control
b.  echo on > /sys/bus/usb/usb2/power/control
3)  /system/bin/r 0xA800430 0x10340
4)  Plug in the USB test fixture
5)  Compliance pattern is generated on the scope

2.3 Rx - Loopback mode
这里的环回表示Link层，不是PHY层的PCS或者PMA环回。
Figure 2-1 USB Rx Test-Loopback

Need a BERT(Bit Error Rate Tester, 误码率测试仪)
Polling.LFPS->65536 Rx.EQ->256 TS1->256 TS2（TS2 Symbol 5 bit2, Loopback）->Loopback

Verilog big endian data, 0xBC means COMMA
Rx.EQ: 32'hBCFF17C0, 32'h14B2E702, 32'h82726E28, 32'hA6BE6DBF, 32'h4A4A4A4A, 32'h4A4A4A4A, 32'h4A4A4A4A, 32'h4A4A4A4A

TS1: 32'hBCBCBCBC, 32'h00004A4A, 32'h4A4A4A4A, 32'h4A4A4A4A

TS2: 32'hBCBCBCBC, 8'h00, {4'h0, 1'h0, loopback > 0, 1'h0, hot_reset_count > 0}, 16'h4545, 32'h45454545, 32'h45454545

2.4 Stream ID
- 同一个端点的MUX机制
- 使用ERDY(Stream ID, NumP)通知host，命令是depcmd，ERDY comes from WUSB

struct usb_request {
[...]
unsigned stream_id:16;
[...]
};

2.5 APL xHCI LTSSM stuck issue
not warm reset yet, waiting 200ms
not enabled, trying warm reset again

This log shows ss port stuck issue.
Disable USB3 roothub port: Clear power Feature and Set BH_Reset Feature.
Disable USB3 non roothub port: Set Rx.disabled Feature.
Add # define DEBUG at the first line of the hub.c file (above the header files) for enabling Linux dynamic debug log.

3 libusb库的使用
Read my blog “Android libusb库的使用”。

4 USB4 v2
借助PAM3调制技术，可实现上行120Gbps（Tx），下行40Gbps（Rx），也即是3Tx+1Rx。

5 URLs
daisho USB
http://www.greatscottgadgets.com/daisho/

LatticeECP (EConomy Plus)
enjoy-digital/usb3_pipe
https://github.com/enjoy-digital/usb3_pipe

[RFC v2 00/22] USB 3.0 hub support & xHCI split roothub for 2.6.38
http://www.spinics.net/lists/linux-usb/msg40949.html

6 Abbreviations
ARC：Argonant RISC Core
AT91SAM9260：SAM means Smart ARM-based Microcontroller
ATMEL SAMBA：ATMEL Smart ARM-based Microcontroller Boot Assistant
DWC2：Design Ware Controller 2，Apple的嵌入式设备，包括iPad和iPhone都是使用的DWC2
EOM: On chip Eye Opening Monitor for USB PIPE PHY receiver side
HUB3CV：USB 3 Hub Command Verifier Ver. 2.1.12.1
ISP1161：Philips' Integrated host Solution Pairs 1161，“Firms introduce USB host controllers”，https://www.eetimes.com/document.asp?doc_id=1290054
LatticeECP: EConomy Plus, integrate USB SerDes
PAM-4：每个符号表示2个bit，眼图有3个眼睛；而NRZ眼图只有一个眼睛
SL811HS：Cypress/ScanLogic 811 Host/Slave，性能上与ISP1161（Integrated host Solution Pairs 1161）相当
TDI：TransDimension Inc.，该公司首先发明了将TT集成到EHCI RootHub中的方法，这样对于嵌入式系统来说，就省去了OHCI/UHCI的硬件，同时降低了成本，作为对该公司的纪念，Linux内核定义了宏ehci_is_TDI(ehci)；产品UHC124表示USB Host Controller；收购了ARC USB技术；现已被chipidea收购，chipidea又被mips收购
TT：Transaction Translator（事务转换器，将USB2.0的包转换成USB1.1的包）
U0：USB SS link is Up
USB BH reset：Bigger Hammer or Brad Hosler，表示warm reset；you may be confused why the USB 3.0 spec calls the same type of reset "warm reset" in some places and "BH reset" in other places. "BH" reset is supposed to stand for "Big Hammer" reset, but it also stands for "Brad Hosler". Brad died shortly after the USB 3.0 bus specification was started, and they decided to name the reset after him. The suggestion was made shortly before the spec was finalized, so the wording is a bit inconsistent.
usb3_mifgen：Altera Memory Initialization File
VNA：Vector Network Analyzer，矢量网络分析仪

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